If I set the library to the HVL library and try to synthesiz open-source-silicon.dev #openlane

If I set the library to the HVL library and try to...

Matthew Guthaus

08/31/2022, 8:20 PM

If I set the library to the HVL library and try to synthesize, I get this failure in synthesis:

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[INFO]: Running Synthesis...
[ERROR]: during executing: "yosys -c /openlane/scripts/yosys/synth.tcl -l /home/mrg/power_test/caravel_test_project/openlane/user_proj_example/runs/22_08_31_13_18/logs/synthesis/1-synthesis.log |& tee /dev/null"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
[INFO]: USING STRATEGY AREA 0

18. Executing ABC pass (technology mapping using ABC).

18.1. Extracting gate netlist of module `\user_proj_example' to `/tmp/yosys-abc-3CzbVV/input.blif'..
Extracted 380 gates and 555 wires to a netlist network with 174 inputs and 67 outputs.

18.1.1. Executing ABC.
ERROR: Can't open ABC output file `/tmp/yosys-abc-3CzbVV/output.blif'.
child process exited abnormally

(I am using the vdda domains for 3.3V+ supplies...)

Matthew Guthaus

08/31/2022, 8:36 PM

The only edit to caravel_user_project is to change: openlane/user_proj_example/config.tcl to use this library: set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hvl"

Matthew Guthaus

08/31/2022, 8:37 PM

There are some errors in parsing the dffs in the hvl library maybe:

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Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrbp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfrtp_1' - skipping.
Warning: Found unsupported expression 'D&!SCE|SCD&SCE' in pin attribute of cell 'sky130_fd_sc_hvl__sdfsbp_1' - skipping.

but dfxtp_1 seems to match fine:

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cell sky130_fd_sc_hvl__dfxtp_1 (noninv, pins=3, area=48.84) is a direct match for cell type $_DFF_P_.

Matthew Guthaus

08/31/2022, 8:38 PM

But it seemed to map them to dfxtp1 which looks fine

Matthew Guthaus

08/31/2022, 8:39 PM

From synthesis log:

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18.1.1. Executing ABC.
Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-ZOxM71/abc.script 2>&1
ABC: ABC command line: "source /tmp/yosys-abc-ZOxM71/abc.script".
ABC:
ABC: + read_blif /tmp/yosys-abc-ZOxM71/input.blif
ABC: + read_lib -w /home/mrg/power_test/caravel_test_project/openlane/user_proj_example/runs/22_08_31_13_22/tmp/synthesis/trimmed.lib
ABC: Reading SCL library from file "/home/mrg/power_test/caravel_test_project/openlane/user_proj_example/runs/22_08_31_13_22/tmp/synthesis/trimmed.lib" has failed.
ABC: ** cmd error: aborting 'source /tmp/yosys-abc-ZOxM71/abc.script'
A

Matthew Guthaus

08/31/2022, 8:40 PM

Yeah, I think the errors are in the dff expression since:

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ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hvl__dfxtp_1".

Matthew Guthaus

08/31/2022, 8:47 PM

I'm suspecting there are errors in the .lib file:

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ABC: Template cannot be found in the template library
ABC: Template cannot be found in the template library
ABC: Table cannot be found
ABC: Memory =    6.88 MB. Time =     0.06 sec
ERROR: Can't open ABC output file `/tmp/yosys-abc-ZOxM71/output.blif'.

Matt Venn

08/31/2022, 8:58 PM

I have to set this:

Matt Venn

08/31/2022, 8:58 PM

set ::env(SYNTH_READ_BLACKBOX_LIB) 1

Matthew Guthaus

08/31/2022, 8:59 PM

@Matt Venn Is that for the instantiation problem in my other thread?

Matthew Guthaus

08/31/2022, 9:04 PM

Ah, yes it does solve that previous issue

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