There is no clock tree. Each block in the chain has a clock input and a clock output. It also re-clocks the data output on the neg edge of the clock so that that it maximizes setup and hold time for the next block to capture on pos edge.

Now it makes sense. In a similar matter, are you doing the same with the latch_enable. The way I see it is, that the FSM could generate a glitch on latch_enable when switching from READ to START ?

tbh, I wouldn't be looking at the current scan controller ... I've completely rewritten it.

Okay, just trying to help ! Keep up the great work !!!

Sure, and much appreciated. I just don't want you to loose time to review something that will be shortly replaced. I'm starting to test the new one and will push as soon as I get it at least doing something that looks good and then you can review that one 😁

I was trapped into the "skew" discussions, so I thought it is a clock tree of the scan clock, but I didn't study the cell logic enough.

Yeah, the idea in the skew talk was that I'd like the clk_out/data_out of each block into the clk_in and data_in of the next block to have about the same delay.

In my design I'm using an additional register with an inverted clock input, which keeps the data out signal stable, when the target register captures it. #JustAThought

Yeah, that's what we do as well.