Where do you see those delays ?
# timing-closuret
tnt
08/31/2022, 11:45 AMWhere do you see those delays ?
t
Tobias Strauch
08/31/2022, 11:55 AMThe path
from signal clk,
through scan_clk_r register,
through the scan_clk_r clock tree,
through the last scan_cell register,
"through the scan_data_in"
through the controller FSM logic (here mux),
to the output_buf[something]_reg
clocked by signal clk,
is what I see in RTL, but I could be totally wrong.