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<@U016EM8L91B> (cc <@U03QSBWN0TU>) I tried to con...
# sky130
s
@Tim Edwards (cc @Rita) I tried to convert a digital subcircuit 
stdcells.spice
to 
stdcells.xspice
using spi2xspice.py:
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python3 <http://spi2xspice.py.in|spi2xspice.py.in>  ~/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib stdcells.spice stdcells.xspice
Of course the location of 
sky130_fd_sc_hd__tt_025C_1v80.lib
liberty file depends on the open_pdks installation. Attached the input spice file and the resulting xspice file. Issues I found: • 
rise_delay
, 
fall_delay
, 
input_load
are set to unreasonable values (1n delays, sometimes 10ns delays in a2d bridges, 1pF input load) • flip-flop and latch spice lines are not translated correctly, the 'Q' net mapping is missing: The following flip flop :
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x2 CLK A RESET_B VSS VSS VCC VCC IQ sky130_fd_sc_hd__dfrtp_1
is translated to:
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A2 A CLK NULL ~RESET_B NULL NULL ddflop
as you can see the 'Q' net is not mapped. Same thing happens for the latch (dlatch):
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x4 A CLK RESET_B VSS VSS VCC VCC IQLATCH net1 sky130_fd_sc_hd__dlrbn_1
translated to:
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A4 A ~CLK NULL ~RESET_B NULL NULL dlatch
• The python script emits .models for d_dff but not for d_dlatch:
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.model ddflop d_dff(ic=0 rise_delay=1n fall_delay=1n)
.model dzero d_pulldown(load=1p)
.model done d_pullup(load=1p)
I added the missing definition:
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.model dlatch d_dlatch(ic=0 rise_delay=200p fall_delay=200p ...)
• Unused inputs (SET if only RESET is used) are connected to a NULL node as well as unused outputs (NegatedQ of flops and latches) I don't know if this works only by coincidence. May be 
NULL
is a special identifier that means Unconnected. From ngspice manual: "_*The literal string ‘null’, when included in a node list, is interpreted as no connection at that input to the model.*_" • Anyway (although not needed as per above) I added a pulldown line to add a ZERO node: 
AZERO ZERO dzero
and used this ZERO node on unused inputs. Unused outputs have been connected to unique 
FLOAT1
, 
FLOAT2
, ... nodes to avoid contentions. • I have added all delay and load parameters for xspice models with reasonable values since defaults are not for a modern vlsi process. Attached the stdcells_fix.xspice with all the manual corrections. @Rita with all above tweaks i was able to simulate a subcircuit with a bunch of digital gates both at transistor level and xspice level, with comparable outputs. Example shown in image is in the xschem_sky130/sky130_tests/test_stdcells.sch
stdcells_fix.xspice
stdcells.spicestdcells.xspice
🙌 2
🍺 1
t
Ideally, the script should generate a separate model line for every instance of every device with the rise/fall/load values unique to that device and incorporating values from the liberty file and potentially incorporating all parasitic wire delays. The values are set arbitrarily to rather worst-case conditions (or possibly worse-than-worst); I can pull them in to be more reasonable. I was not aware of the missing model for the latch, and can add that to the script. I will have to debug the missing Q net value. It is proper to leave unused SET and RESET as NULL---A NULL value indicates that the flop does not have the pin.
@Stefan Schippers: The timing values are defaults and are not really for any specific process; they are meant to be passed on the command line.
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#   -io_time=<value>  Rise and fall time for signals in and out of the digital block
    #   -time=<value>     Rise and fall time of gate outputs
    #   -idelay=<value>   Input delay at gate inputs
    #   -odelay=<value>   Throughput delay of the gate
    #   -cload=<value>    Gate output load capacitance
In the qflow installation in sky130 from open_pdks (which is maybe usable with the OSU standard cells but definitely not with the SkyWater standard cells), I specified the following options to be passed to spi2xspice.py:
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set xspice_options="-io_time=500p -time=50p -idelay=5p -odelay=50p -cload=250f"
s
Thank you, that fixes many things 🙂 the missing Q is probably due to the insane port order of standard cells? (supply /body pins between inputs and outputs)
t
I'm not sure what's going on there and I'll have to debug it.
s
@Tim Edwards does the script work also for a (hierarchic) digital subcircuit that contains subcircuits? or do I need to apply the script to any subcircuit separately?
t
@Stefan Schippers: As written, it does not handle hierarchy. I'm not even sure how xspice works with hierarchy. Does it work to pass a digital signal to a subckt call? I don't think I've ever tried it.
s
ok thanks.
t
If you want to give it a try, just send me a working simple example and I'll expand spi2xspice.py to match.
s
will take the challenge, although i expect al 1% success probability :-)
t
@Stefan Schippers: I found the error in generating the output nodes; the sky130 liberty files put double quotes around pins everywhere, and those have to be stripped or else the pin names won't compare to the pin names in the SPICE netlist. I have corrected the error in the qflow repository and pushed the fix to opencircuitdesign.com.
s
Thank you !
btw i have tried any combination of node names (as a vector, no vector, explicit list, with %d specifiers, everything) to wrap a d_lut gate into a subckt and use it , it either causes a simulator error or gives no results. So I must conclude AFAIK hierarchy is not implemented with digital nodes.
I believe it is not a fundamental limitation of the simulator core, the netlist is flattened before building the matrices, so it is a parser problem that does not understand the syntax (or I do not provide the right syntax)
@Tim Edwards this works!
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.subckt nand2_wrapper A B out
A1 [A B] out d_lut_sky130_fd_sc_hd__nand2_1
.ends

.subckt stdcells a_QLATCH a_A a_X a_B a_Y a_CLK a_Q a_RESET_B a_XSCHEM a_VCC a_VSS

...
AA2D1 [a_A] [A] todig_1v8
AA2D2 [a_B] [B] todig_1v8
...
...
XA1 A B IX nand2_wrapper
.ends
...
.model d_lut_sky130_fd_sc_hd__nand2_1 d_lut (rise_delay=200p
+ fall_delay=200p input_load=10f table_values "1110")
The netlist parser just flattens the hierarchy and doesn't care if subcircuit nodes are analog or digital. After netlist expansion the nand2 call (from subcirtcuit stdcells instantiated in top as X1):
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a.x1.xa1.a1 [ x1.a x1.b ] x1.ix d_lut_sky130_fd_sc_hd__nand2_1
🌏 1
t
That was fast. Now I have extra work to do. . .
s
Yes i realized that there is no true hierarchy in ngspice, there is a netlist preprocessor that flattens it out, and it operates at a semantic level. The only caveat is that [A B ...] vector ports must only be used at tle lowest level, the one that directly calls code models. Other than that the preprocessor really doesn't care if nodes that are passed are digital or analog.
m
this is great ! I really want better mixed signal sims
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