tnt
08/30/2022, 1:03 PMsub[N-1:0] with a_in / b_in input ports and a_out / b_out output ports and they're all chained a[N-1:0] an b[N-1:0] . Is there a way to write a SDC so that the delay from a_out to the next block a_in and the delay from b_out to the next block b_in are within some margin of each other ?Ryan R
08/30/2022, 5:14 PMTom Spyrou
08/30/2022, 7:42 PMTom Spyrou
08/30/2022, 7:42 PM