<@U016EM8L91B> Is it safe to assume default wishbo...
# caraveld
Dinesh A
08/30/2022, 9:39 AM@Tim Edwards Is it safe to assume default wishbone clock is 25ns/40Mhz?
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Tim Edwards
08/30/2022, 1:04 PMThat's the absolute maximum clock rate for the VexRISC processor. The typical value is 10MHz, which is the rate of the clock on the development board. As a timing constraint, using 25ns is the most obvious choice.
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Dinesh A
08/30/2022, 3:27 PMIn Default caravel waveform without any VexRISC flash access, i see wb clock is 40Mhz, How the boot up frequency is controlled ?
Dinesh A
08/30/2022, 5:02 PMSorry, This clock is driven in test bench at port clock Pin. Initially I thought we are booting with internal PLL.
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