Hello everyone. I am developing an OTA design. Wit...
# analog-design
w
Hello everyone. I am developing an OTA design. With open-loop simulations a gain of ~43 dB and BW of ~214 KHz with no load are obtained. Nonetheless, I made a closed-loop simulation as shown in the image. The gain is given by capacitors ratio (3 pF/92 fF), so the closed-loop gain should be ~30 dB. But, it doesn't work. VCM voltage is 0.9 V but Dc level in output is 1.8V. Any ideas or suggestions about what's happening. This question is very specific, but I know that this channel has many people experienced in analog designs.
l
Your input pins are swapped They are ok...
k
Hi I've used a testbench form the repo of @Weston Braun https://github.com/westonb/open-pmic and it worked for me so You can give it a try. In fact the design was silicon proven and worked.
w
Pretty sure inp and inm are swapped? If inp is > inm the current through [M1, M3, M5, M7, M8] will all be less, which will pull the output down.
as the input pair is PMOS
w
So, the feedback and vin signal must be in the other input?
w
Your inp and inm pins are named incorrectly. They need to be flipped.
I am pretty sure? Work through a test case like I did. If inp > inm then the current through M2 will be greater than the current through M1
M2 gets mirrored to the pull down, M6, while M1 gets mirrored to the pull up, M8. So that would case the output to go low.
w
So, are you saying that order is this?
What you said makes sense. I got a better result now, although it's still not close to what I expected.
w
You have a pretty complicated feedback network. Just try with a gain of 1 non inverting amplifier or something.
Also, have you characterized the Gm of the amplifier? You can do that by measuring the open loop gain with the output shorted. And measuring the output current
The OTA has an output resistance of the current mirrors, which is going to be relatively low. something in the 10's of k ohms?
and you have an output pole determined by C1 and Gm
w
This is my testbench of open-loop gain.
I simulate with load capacitor of 2pF and I get a similar result.
s
@wisla morais before doing a .ac simply run a .op simulation, that gives the dc voltage of all nodes. Check if all node voltages are reasonable. In DC the circuit act as a unity gain buffer so
out
should be close to
vcm
. From the images the input pins of the OTA are swapped. I blieve this is fixed now according to above comments. I suspect that 0.9V headroom (vdd -vcm) for
01v8
pfets is not enough. try to replace the input pair pfets with
01v8_lvt
and/or lower vcm value.
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w
Yes, the inputs were switched. And now the dc level of the inputs and output is about 0.9V.
s
Try to replace 01v8 pfets of the input pair of the ota with 01v8_lvt and make them somewhat bigger (higher W). That will improve the gain.
w
Okay @Stefan Schippers. Thank you for the suggestion.
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@Weston Braun with tf command (
tf v(out) vp1
) output resistance returned by ngspice is 3 M ohms.
s
The OTA is biased at low current, 1.5uA, The 10MEG feedback resistors is not negligible if compared to OTA output resistance. This will reduce the overall gain.
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w
Thank you very much for your help, suggestions and for clarifying some doubts.
s
@wisla morais see the problem. With 0.9V on input stage the differential is not working The sources of the input 01v8 transistors are at 1.798V, so the current source transistor is in linear region.. See the 1.5uA current is not mirrored into the differential amplifier, it is working with 37nA
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replacing the input pair with bigger and _lvt transistors the mirrored current into differential will be 1.47uA, so close to 1.5uA. Not ideal yet, but far better than before...
with the above modification this is the gain plot. Not 30dB but better than before :-)
maximum gain is limited by the 10MEG resistors that are not negligible considering the low OTA bias current (thus high output resistance) and also due to the 2pF output load capacitor.
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w
I really appreciate your help @Stefan Schippers. I will consider all the improvements suggested by you in my project. I sized the transistors not to operate in the weak inversion, because I saw that PMOS transistor from the open-PDK behave strangely in this inversion region. Thinking about it, the sizing was not very good, the input pair was small. I will improve this with your tips. Thank you.
b
Yes, you should avoid weak inversion; the current models are bad in that region. We are waiting for a fix.
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w
Right @Boris Murmann. Thank you for confirm for me.
l
This topology should use pseudo resistors. They have resistances close to teraohms for a small voltage swing (< 400 mV). See the article from Reid Harrison. https://ieeexplore.ieee.org/abstract/document/1201998
w
Yes @Luis Henrique Rodovalho thank you. I will study more about pseudo resistors. I'm trying to use them in my simulation. But I have a problem, because I'm using single-supply (1.8V) so I must consider the common mode voltage (VCM) and in the articles I saw the authors used split-supply.
l
Try this. For your case, if you use pseudo resistors, a resistor ladder is enough, but you should use a resistor ladder plus an opamp in buffer configuration. https://www.ti.com/sc/docs/msp/papers/1998/gustaf.pdf
w
So, do I need to use an buffer to isolate the non-inverting input and avoid loading it?
l
Yep. It is not really needed for this configuration with pseudo-resistors, because the current that passes through it would be in the order of pA. Even for your case, with 10 MegOhm resistors, a resistor ladder alone could be enough. Anyway, if you use anything like a non-inverting amplifier, or a differential voltage amplifier, you will need a buffer to make this virtual ground.
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w
Right. I appreciate your help @Luis Henrique Rodovalho, thank you.