Run report_disabled_edges to make sure the clock t...
# timing-closuret
Tom Spyrou
08/29/2022, 7:19 PMRun report_disabled_edges to make sure the clock tree is not broken by loops. If report_checks does not show any paths then the design is completely unconstrained.
m
Matt Venn
08/29/2022, 7:31 PMAt top level caravel or for the small designs? And how to run the report?
Also the scan chain clock is generated by scan controller, it's not the top level caravel/wishbone clock
Matt Venn
08/30/2022, 11:01 AM@Tom Spyrou can you clarify?
Matt Venn
08/30/2022, 11:02 AMWith the work tnt has done the thing I want most is help with a caravel level sdc file for checking the scan chain with all the small designs
t
Tom Spyrou
09/01/2022, 11:51 PMyou can run report_disabled_edges on any design. Just modify the openroad script in openlane and add it right after synthesis in the synthesis tcl or in the final report tcl. That way it will run for your block runs and the top run. You can also run check_setup in those same scripts to do sanity checks on the SDC.
Tom Spyrou
09/01/2022, 11:51 PMcheck_setup [-verbose]
[-unconstrained_endpoints]
[-multiple_clock]
[-no_clock]
[-no_input_delay]
[-loops]
[-generated_clocks]
[> filename]
[>> filename]
-verbose
-unconstrained_endpoints Show offending objects rather than just error counts.
Check path endpoints for timing constraints (timing
check or set_output_delay).
Check register/latch clock pins for multiple clocks.
Check register/latch clock pins for a clock.
Check for inputs that do not have a set_input_delay
command.
Check for combinational logic loops.
Check that generated clock source pins have been
defined as clocks.-multiple_clock
-no_clock
-no_input_delay -loops
-generated_clocks The check_setup command performs sanity checks on the design. Individual checks can be performed with
the keywords. If no check keywords are specified all checks are performed