open-source-silicon.dev

hi,i am tring to harden my design after RTL verification and GL, when i run `make XXX` ,it has a error: `4. Executing HIERARCHY pass (managing design hierarchy).`

`4.1. Analyzing design hierarchy..`
ERROR: Module `\BlockRAM_1KB' referenced in module `\eFPGA_top' in cell `\Inst_BlockRAM_5' is not part of the design.
`child process exited abnormally` ,RTL and GL has passed, where  i need to check?

`../../verilog/includes/includes.rtl.caravel_user_project` has include the file `BlockRAM_1KB.v`

`BlockRAM_1KB` is defined as BLACKBOX_FILES or not? Check file path

in this `BlockRAM_1KB`,quote a blackbox module like `(*blackbox*) module XXX(...)XXX;endmoudle` ,when i delete the code `(*blackbox*)` ,run the RTL and `make XXX` again, it still not work and the same error? Or what should i do? i dont find somewhere defien it as a blackbox file

ok,it generates a wrong hierachy.dot which cannot be opened with the message `syntax error in line 189 scanning a quoted string (missing endquote?no longer than 16384?)` ,i will check the step before