Hi , i have created a verilog wrapper file with my analog macro inside it...And in the openlane i am feeding the LEF , LIB and GDS....But flow errors out... The LEF is written from magic. What i suspect is that the tool is not able to TAP the pin Any guidelines on how to create pins of the macros ?? particular width / hegith needed ?? LMK what are all info /files required [STEP 19] [INFO]: Running Global Routing... [INFO]: Starting FastRoute Antenna Repair Iterations... [STEP 20] [INFO]: Running Fill Insertion... [STEP 21] [INFO]: Writing Verilog... [STEP 22] [INFO]: Running Detailed Routing... [ERROR]: during executing openroad script /openlane/scripts/openroad/droute.tcl [ERROR]: Exit code: 1 [ERROR]: full log: designs/AMUX_wrapper/runs/RUN_2022.08.28_12.23.54/logs/routing/22-detailed.log [ERROR]: Last 10 lines: [INFO DRT-0033] via2 shape region query size = 1920. [INFO DRT-0033] met3 shape region query size = 1454. [INFO DRT-0033] via3 shape region query size = 1920. [INFO DRT-0033] met4 shape region query size = 511. [INFO DRT-0033] via4 shape region query size = 16. [INFO DRT-0033] met5 shape region query size = 26. [INFO DRT-0165] Start pin access. [ERROR DRT-0073] No access point for U_AMUX_8x1_20_08_layout/V4. Error: droute.tcl, 46 DRT-0073 child process exited abnormally

file a github issue in openlane with reproducible test case

ok

The message

[ERROR DRT-0073] No access point for U_AMUX_8x1_20_08_layout/V4.

seems to indicate that the

V4

pin of

U_AMUX_8x1_20_08_layout

can not be routed. Can you check the layout (LEF/DEF)? Maybe moving the macro will help.

@Mitch Bailey - i have just created a wrapper over analog and let the tool do the PNR....

"GDS_FILES_OPT" is not the parameter you shold be using its EXTRA_GDS_somethingsomething The extra GDS does not need the pdk cell, only extra GDS. 1. Also the error might be related to the pin being missaligned on the manufacturing grid (5nm grid). 2. It might have different direction that the layer. E.g. Met1 pins need to be horizontal. Met2 needs to be vertical 3. Make sure the cell placement is inside DIE area. use or_gui to debug this. 4. LEF needs to match the GDS. How did you generate it?

Manual placement might work better for hard macros.

1. Also the error might be related to the pin being missaligned on the manufacturing grid (5nm grid). -- RY: but DRC is clean on the design 2. It might have different direction that the layer. E.g. Met1 pins need to be horizontal. Met2 needs to be vertical . RY: Let me check 3. Make sure the cell placement is inside DIE area. use or_gui to debug this. - YEs it is, I opened the final GDS and the macro is placed in the corner. 4. LEF needs to match the GDS. How did you generate it? - lef write -hide command from magic

You only need the pin shapes and width and the directions to be followed. Blockage are not needed.

For macro placement example, see.

user_project_wrapper/config.tcl

## Internal Macros
### Macro Placement
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg

@Arman Avetisyan - whats the values for the width ? llike mutiples of the min width will do ? let me check the directions assigned

What you mean "direction assigned"? the pins just need to be longer in direction of the metal. The LEF direction might also be important to check. Min width is okay, or double that

direction assigned means what openlane follows as horizontal or vertical for diff met layers