I have some questions about layouting best practices, not sure if here is the place for this, but: 1. Should vias be built as matrix of squares or shuld they fill all the available area? As an example, I am routing the drain of a FET out to a resistor going from metal1 to metal2 just over the transistor area, should I draw via1 as a big rectangle over the entire area or place multiple 0.26x0.26 squares inside a metal1/metal2 rectangle? 2. Should I avoid routing over the transitor active area, even on metal2? 3. Do metal/via overlap need to be only in one direction? DRC points its ok if I draw the metals extending only in one direction, should I always trust that if DRC is ok it will work? 4. Via/metal current limits per area, where to find them? Thanks in advance! Maybe I should post this on sky130? Don't know if these things are specific or just general IC layout practices.

1. Multiple squares inside M1 and M2 2. You shouldn't need to worry about routing over the transistor. 3. Not exactly sure what you mean by this, a picture would be nice. 4. I haven't seen any current density rules for sky130 and I believe these at least somewhat process dependent.

Hello Sam, thank you for the answers. If you dont mind: 1. The transistors generated by the sky130 PDK tools use some kind of elongated (see attachment) vias from local interconnect to the substrate in their guard rings. Is this a different situation? a. Also, If I am using multiple squares, should I always use minimum dimensions? If you could point a reason for this it would be nice too, since the DRC allows larger vias and I am not space constrained.

Huh, I'm used to the commercial tools and haven't seen an elongated via like that (I'm more familiar with other PDKs where that would definitely be a DRC violation). Someone else might have better insight on this. For the via, I think the one dimension overlap is fine given my understanding of the DRC rules here: https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html#via (via.5{a,b,c})

Great info, thank you for your help. I will dive a little deeper in the docs, and maybe forward this question to the sky130 group

1. Depends on technode mostly. IDK if rectangles of non standard sizes are supported. Check if it passedls DRC 2. If you want to avoid parasitics or you have ESD issues. 3. Depends on the tech. Skywater docs specify the answer 4. tech lef has maximum current density data at 90 degrees.

1. I think Magic does it work Sky130 in the way that you design a big rectangle and Magic will automatically fill it with an optimized matrix of squares accordingly when exporting GDS

I still didnt make it to GDS, but this would be great to know