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<@U016EM8L91B> I have a `~900um` met4 wire that is...
# sky130
a
@Tim Edwards I have a 
~900um
met4 wire that is attached to a small gate (
0.126um
). OpenROAD wants to insert 56(!) antenna diodes. If I read it right, the tech LEF says adding diodes past 
0.0225um
of diffusion makes very little difference.
Copy code
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
My antenna violation is about 12000, and the 
ANTENNADIFFSIDEAREARATIO
statement says we want about 
22.5um
of diffusion, so with each diode_2 having `0.4347um`of diffusion, that does mean 50+ diodes.
Do you know if the values in the 
ANTENNADIFFSIDEAREARATIO
statements are correct?
t
They're correct, although whether they are realistic is another question.
I have also discussed a similar problem with @Matt Liberty. I remember studying this issue in detail but it was a long time ago and I have forgotten all the details. I guess it makes some sense, though, that a diode sinks charge through the reverse-biased P-N junction, which is a pretty small amount of current, and that P-N junction has to sink charge faster than the charge builds up on the antenna wire. The "hack" solution that I came up with when talking to Matt is to just add a dummy buffer (bigger than minimum strength) to the wire so that the amount of gate area increases. In the example Matt and I were looking at, the problem occurred on a net that fed an output buffer of the digital block, and the likely root cause of the antenna issue was twofold: (1) The constraints on the pin load were too small, causing the resizer to leave the digital block's output buffers at minimum size, and (2) The pin position was probably constrained in such a way that the pin was forced to be placed far away from the circuitry driving it, causing the internal route to be much longer than necessary. Forcing the synthesis tool to assume something like a 1-2pF load on all digital block outputs would have resulted in a much larger gate with much larger input transistors, and the antenna ratio on the internal net would be much lower.
m
As both users are using a caravel harness it seems that external pin loads should be handled automatically in that case. Is this something that OL can handle to avoid more of these?
t
I think that the OL default for pin capacitance loading should be much higher than it is (apparently; I haven't looked up what it is set to).
m
Couldn't we know the exact values for caravel?
t
True, those can be computed from the top-level layout. Where would that information need to be put?
I'm more used to assuming nothing about the top level and applying a generous default value.
m
../configuration/README.md\040:| 
SYNTH_CAP_LOAD
| The capacitive load on the output ports in femtofarads. <br> (Default: 
33.5
ff)|
Where did 33.5 come from?
the README is not really correct either as the value comes from the config.tcl in OL and vaies by library
t
I'm not the person to answer questions about what default values were put in openlane. The value suggests that maybe it's based on the input capacitance of a typical small buffer gate input or something like that, which is way too low for a default assumption.
m
that's the value from sky130_fd_sc_hd
a
Unfortunately that wont fix my issue, which is just a long met4 wire feeding a hold buffer. I presume that explains the small gate area, since a hold buffer is designed to be slow.
t
@Anton Blanchard: You can, however, insert a buffer in the verilog hanging off of that net and with output to nowhere, just to add gate area to that net.
m
It is odd to have a long wire on a hold critical path, usually they are quite short. Is this some clock skew consequence?
a
@Tim Edwards Good point, however we don't have a good way to make manual netlist modifications post synthesis in Openlane, and I'm not sure how I'd even identify them all reliably (there are quite a few). Perhaps we should add this as an option to the OpenROAD antenna repair based on some heuristic (gate area or number of antenna diodes required to fix the violation)
@Matt Liberty It might be another side effect of my clock skew issues, let me try and understand it
@Matt Liberty I just checked, and the other examples are not hold buffers, but are 1x strength cells, so are all the smallest gate area cells
m
the 1x cells are the fanouts of long wires?
a
Yeah
m
@Anton Blanchard Can you provide a test case in an issue?
a
@Matt Liberty I opened https://github.com/The-OpenROAD-Project/OpenROAD/issues/2207 for us to track it
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