Hi @Mitch Bailey, I'm attempting to make a simple inverter to get familiar with the opensource workflow but getting stucked with LVS. Current situation is the circuits and netlists match but the subcircuit pins does not. The columns under the subcircuit pins has another duplicate of pin names while the other has no matching pin. The layout spice file is generated with ext2spice hierarchy on. I'm not sure whether I'm doing LVS correctly nor how to correct it. Please find the Netgen LVS output, comp.out, spice files for inverter layout(CMOS_INV) and schematic (INV_VP_VN) in the attachment. Thanks in advance!

@JC Regenerate your schematic netlist according to Stefan's instructions. (see next post). I don't think you need to worry about the port order.

@Mitch Bailey and @Stefan Schippers, thank you! I will give that a shot and report back.

@JC if you look at the spice netlists the pfet and nfet are instantiated as subcircuits. Nothing tells the LVS tool how these subcircuits are defined. You probably need to include the spice .lib file, as you also do for simulations. This is my guess, may be @Mitch Bailey can confirm or if not, tell you how this is normally handled in LVS checking.

nfet and pfet are considered parameterized black box subcircuits in the current skywater pdk LVS.