hi @Tim Edwards, wanted to clarify the correct commands usage (finally !) for pex from magic . I am flattening the design . There are two sets of commands i tried : SET1 (got from one of the threads) : file pex_layout_flat_ABC.spice set NAME [cellname list self]; select top cell; # (Flattening improves resistance extraction) flatten "[list $NAME]_flat" load "[list $NAME]_flat" select top cell; extract do resistance; extract all; ext2sim labels on; ext2sim; extresist tolerance 10; extresist all; ext2spice lvs; ext2spice cthresh 0; ext2spice extresist on; ext2spice -o "pex_[list $NAME].spice"; SET2 : set NAME [cellname list self]; select top cell; flatten "[list $NAME]_flat" load "[list $NAME]_flat" select top cell; extract all ext2spice cthresh 0; ext2spice rthresh 0; ext2spice The SET1 is giviing Resistance values 'R' along with 'C' . But in SET2 , only 'C' is dumped. Which one is correct ? My post layout simulation works with SET2 , and not with SET1. LVS is clean in my case , hence expect same post layout results. Thanks @Mitch Bailey

They're both correct; depends on whether you want C parasitics or R-C parasitics. Note that "ext2spice rthresh 0" produces "lumped" resistances which no tool that I know of knows how to deal with (although it's a clever idea, at least for a 1st-order approximation of wire delays).

@Tim Edwards - confused now. there is no R dumped in SET2 - so no lumped resistance too . Is it SAFE to tapout with SET2 set of commands for extraction + post-layout simulation ?

Depends on how sensitive your circuit is to wire resistance. When you say your simulation doesn't work with the R-C extracted netlist, is that a failure to get the right answer, or a failure to start or complete the simulation?

@Tim Edwards - any tips on how to debug ? When there are crosscoupled circuits - do the -RC extraction create issues ? I am just guessing since another design with R-C extraction did work. Do internal node initial condition cause any issue ?

It's hard to give you an answer because I still don't know in what way your simulation is failing.

Let me check a bit more if i can clues about the wire sensitivity ....

Can you identify where in the layout these are (maybe check the mag file - remembering you might have to divide the coordinates by 200)? The mag file might also have a clue as to what layers these were extracted from.

let me check

I'm not sure that there is anywhere that the positions of the intermediate nodes like

.n1

and terminals like

.t1

are spelled out. Note that magic attempts to solve a very complicated geometry problem and will try to reduce the resistor networks it detects, but the simplification is not necessarily that easy, and you might get high resistance paths that are parallel to low resistance paths; you'd have to draw out the resistor network to figure out if that's true or not.