open-source-silicon.dev

<@U016ULGAUNM> Hi, I opened a new <https://github.com/google/skywater-pdk-sky130-raw-data/issues/17|issue> about the noisy PFET data.

image.png

```* PMOS diode testbench

* Include SkyWater sky130 device models
.lib "/usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
.param mc_mm_switch=0

X0 D G S B sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1.0 l=0.5 m={1}

VG G 0 -1
VS S 0  0
VD D G  0
VB B 0  0

.option gmin = 1e-15
.control
	dc VG -2.0 -0.1 1m
	let vgs = abs(v(g)-v(s))
	let id  = abs(i(vd))
	let gm  = abs(deriv(id)/deriv(vgs))
	let gmid = gm/id
	plot id vs vgs
	plot id vs vgs ylog ylimit 1e-15 1e-3 
	plot gmid vs id xlog
.endc

.end```
The transistors seems to be fine.

Hi <@U01QTMG2K8R> thanks for sharing this info.
In this thread I'm trying to share that the raw pmos data is noisy, so the model might not be helpful when using it to predict what a real device will do.
For, the model itself, the main red flag is the knee at 10uA in the gm/ID plot; gm/ID should be mostly monotonic within 10^-15A to 10^-5A. I could have made a mistake, so please provide helpful information if you have it. I also ran your simulations with an NMOS, it doesn't show that knee in the plot, I think that is an indicator of a more realistic device.
```* NMOS diode testbench

* Include SkyWater sky130 device models
.lib "/usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
.param mc_mm_switch=0

X0 D G S B sky130_fd_pr__nfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1.0 l=0.5 m={1}

VG G 0 1
VS S 0  0
VD D G  0
VB B 0  0

.option gmin = 1e-15
.control
	dc VG 0.1 2.0 1m
	let vgs = abs(v(g)-v(s))
	let id  = abs(i(vd))
	let gm  = abs(deriv(id)/deriv(vgs))
	let gmid = gm/id
	plot id vs vgs
	plot id vs vgs ylog ylimit 1e-15 1e-3 
	plot gmid vs id xlog
.endc

.end```


That knee gets even worse for smaller lengths. This is your simulation for l=150nm

This knee is the result of non-idealities, because VDS is too high. The transistors must be characterized in the linear region. See <https://www.mdpi.com/2079-9268/12/2/34> . It uses the ACM compact model, but the same characterization scheme can be used for EKV.

```* PMOS diode testbench

* Include SkyWater sky130 device models
.lib "/usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
.param mc_mm_switch=0

X0 D G S B sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1.0 l=0.5 m={1}

VG G 0 -1
VS S 0  0
VD D 0 -0.013
VB B 0  0

.option gmin = 1e-15
.control
	dc VG -2.0 -0.1 1m
	let vgs = abs(v(g)-v(s))
	let id  = abs(i(vd))
	let gm  = abs(deriv(id)/deriv(vgs))
	let gmid = gm/id
	plot id vs vgs
	plot id vs vgs ylog ylimit 1e-15 1e-3 
	plot gmid vs id xlog
.endc

.end```


```* PMOS diode testbench

* Include SkyWater sky130 device models
.lib "/usr/share/pdk/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
.param mc_mm_switch=0

X0 D G S B sky130_fd_pr__pfet_01v8 ad=4e+11p pd=2.8e+06u as=4e+11p ps=2.8e+06u w=1.0 l=0.5 m={1}

VG G 0 -1
VS S 0  0
VD D 0 -0.013
VB B 0  0

.option gmin = 1e-15
.control
	dc VG -2.0 -0.1 1m
	let vgs = abs(v(g)-v(s))
	let id  = abs(i(vd))
	let gm  = abs(deriv(id)/deriv(vgs))
	let gmid = gm/id
	plot id vs vgs
	plot id vs vgs ylog ylimit 1e-15 1e-3 
	plot gmid vs id xlog

	dc VD -2.0 -0.1 1m
	let vds = abs(v(d)-v(s))
	let id  = abs(i(vd))
	plot id vs vds

.endc

.end```
See, there is very low rds, due to the small transistor length. That is why the transistors must be characterized in the linear region.