open-source-silicon.dev

image.png

Hi,  when I used netgen tool for LVS, it can work for flatten netlists. However, it can not work for hierarchical netlists, as shown . How I can fix it?, can you give me some tips?. I hope my question is clear

how it supposed to know which cells to compare. The arguments need to look like: nelist_name subckt_name

The flatten netlist should not be used because its missing pins, therefore pin checks

<@U03ED7UNVFH>:  For the hierarchical case, use the syntax `lvs "&lt;file1_name&gt; &lt;subckt_name&gt;" "&lt;file2_name&gt; &lt;subckt_name&gt;" [&lt;options&gt;]`.  If you just provide a file name, then netgen sees subcircuits but does not see those subcircuits instantiated anywhere, and so its understanding is that it is looking at a library of subcircuit components and not a netlist.  You have to tell it what subcircuit is to be considered the top level of the design.