Belal Ali
08/20/2022, 12:01 PMLuis Henrique Rodovalho
08/20/2022, 2:32 PM* inverter testbench
.include "../../../gf180mcuA/libs.tech/ngspice/design.ngspice"
.lib "../../../gf180mcuA/libs.tech/ngspice/sm141064.ngspice" typical
.include "../magic/inv.spice"
vdd vdd 0 3.3
vss vss 0 0
vin in vss 0
x0 in out vdd vss inv
.control
dc vin 0 3.3 1m
plot in out
plot db(abs(deriv(out))) vs out
.endc
* NGSPICE file created from inv.ext - technology: gf180mcuA
.subckt inv in out vdd vss
X0 out in vdd vdd pmos_3p3 w=1.8u l=0.6u
X1 vdd in out vdd pmos_3p3 w=1.8u l=0.6u
X2 out in vss vss nmos_3p3 w=0.6u l=0.6u
X3 vdd in out vdd pmos_3p3 w=1.8u l=0.6u
X4 vss in out vss nmos_3p3 w=0.6u l=0.6u
X5 out in vdd vdd pmos_3p3 w=1.8u l=0.6u
X6 vss in out vss nmos_3p3 w=0.6u l=0.6u
X7 out in vss vss nmos_3p3 w=0.6u l=0.6u
C0 vdd in 0.50fF
C1 out in 1.16fF
C2 vdd out 0.55fF
.ends