Hi @Tim Edwards, after extract all , i get message "Total of 25 warnings." -- where can i view these warnings ? Also is there any reporting can be done - to check whether i have any undriven terminal / instance pins in the layout ? Thanks

Try

feedback why

after

extract all

@Mitch Bailey Tried , but its giving no output... Now i am facing another strange thing...I have 4 labels V1 , V2 , V3 , V4 -- But only V3 is getting extracted as a top level port in spice netlist>>>> _------------------------------------ Selected mask layers: metal1 ( Topmost cell in the window ) via1 ( Topmost cell in the window ) metal2 ( Topmost cell in the window ) via2 ( Topmost cell in the window ) metal3 ( Topmost cell in the window ) Selected label(s): "V1" is attached to via2 in cell def AMUX_8x1_19_08_layout "V2" is attached to via2 in cell def AMUX_8x1_19_08_layout "V3" is attached to via2 in cell def AMUX_8x1_19_08_layout "V4" is attached to via2 in cell def AMUX_8x1_19_08_layout ----------------------------------- .subckt AMUX_8x1_19_08_layout V5 S1_MUX S0_MUX S2_MUX VSS VDD_HIGH VDD_LOW OUT V6 + V3 V8 .ends

Anything on your screen messages as you extract?

Not really % extract all Extracting sky130_fd_pr__pfet_g5v0d10v5_CG94UW into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__pfet_g5v0d10v5_CG94UW.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_A3ZYGX into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__nfet_g5v0d10v5_A3ZYGX.ext: Extracting MV_5V_pmosTap_substrate into /home/ratul619/IIT_study_VM/magic/sky130_layouts/MV_5V_pmosTap_substrate.ext: Extracting MV_5V_nmosTap_substrate_Pwell into /home/ratul619/IIT_study_VM/magic/sky130_layouts/MV_5V_nmosTap_substrate_Pwell.ext: Extracting inv_D1_W0p840_L0p5_10_7 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/inv_D1_W0p840_L0p5_10_7.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_VJVYG6 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__nfet_g5v0d10v5_VJVYG6.ext: Extracting and_D1_W0p840_L0p5_10_7 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/and_D1_W0p840_L0p5_10_7.ext: Extracting decoder_D1_g5d10_10_07 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/decoder_D1_g5d10_10_07.ext: Extracting V_SEL_g5D10_W0p840_L0p5_11_7_layout into /home/ratul619/IIT_study_VM/magic/sky130_layouts/V_SEL_g5D10_W0p840_L0p5_11_7_layout.ext: Extracting decoder_4x1_with_pmos_switch_LV_support_11_07_layout into /home/ratul619/IIT_study_VM/magic/sky130_layouts/decoder_4x1_with_pmos_switch_LV_support_11_07_layout.ext: Extracting sky130_fd_pr__pfet_g5v0d10v5_HDJJAB into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__pfet_g5v0d10v5_HDJJAB.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_PDTLGW into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__nfet_g5v0d10v5_PDTLGW.ext: Extracting sky130_fd_pr__pfet_g5v0d10v5_54DD5S into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__pfet_g5v0d10v5_54DD5S.ext: Extracting sky130_fd_pr__nfet_g5v0d10v5_RU632G into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__nfet_g5v0d10v5_RU632G.ext: Extracting inverter_D1_g5v10 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/inverter_D1_g5v10.ext: Extracting sky130_fd_pr__pfet_01v8_6PK3KM into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__pfet_01v8_6PK3KM.ext: Extracting sky130_fd_pr__nfet_01v8_FNPZCM into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__nfet_01v8_FNPZCM.ext: Extracting LV_1v8_pmosTap_substrate into /home/ratul619/IIT_study_VM/magic/sky130_layouts/LV_1v8_pmosTap_substrate.ext: Extracting LV_1v8_nmosTap_substrate_Pwell into /home/ratul619/IIT_study_VM/magic/sky130_layouts/LV_1v8_nmosTap_substrate_Pwell.ext: Extracting inv_D1_1v8 into /home/ratul619/IIT_study_VM/magic/sky130_layouts/inv_D1_1v8.ext: Extracting VLS_g5D10_LV1v8_HV5V into /home/ratul619/IIT_study_VM/magic/sky130_layouts/VLS_g5D10_LV1v8_HV5V.ext: Extracting VLS_1v8to5V_D1_And_VoltSelector_1407_layout into /home/ratul619/IIT_study_VM/magic/sky130_layouts/VLS_1v8to5V_D1_And_VoltSelector_1407_layout.ext: Extracting sky130_fd_pr__pfet_g5v0d10v5_HKHHPX into /home/ratul619/IIT_study_VM/magic/sky130_layouts/sky130_fd_pr__pfet_g5v0d10v5_HKHHPX.ext: Extracting HV_TG_GATE into /home/ratul619/IIT_study_VM/magic/sky130_layouts/HV_TG_GATE.ext: Extracting VLS_1x2_1708_layout into /home/ratul619/IIT_study_VM/magic/sky130_layouts/VLS_1x2_1708_layout.ext: VLS_1x2_1708_layout: 16 warnings Extracting AMUX_8x1_19_08_layout into /home/ratul619/IIT_study_VM/magic/sky130_layouts/AMUX_8x1_19_08_layout.ext: Total of 16 warnings. % ext2spice lvs % ext2spice exttospice finished.

Try

feedback save ext.results

@Mitch Bailey, i fixed the shorts problem.... But getting some errors like below -- are they ok to have ?? Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Combined 7 parallel devices. Resolving automorphisms by pin name. Netlists match with 149 symmetries. Circuits match correctly. There were property errors. VLS_16x2_1808_layout_WIRE_EXT_0//VLS_16x2_1708_layout_1//VLS_1x2_1708_layout_0[0]//VLS_1v8to5V_D1_And_VoltSelector_1407_layout_0//VLS_g5D10_LV1v8_HV5V_1//inverter_D1_g5v10_0//sky130_fd_pr__pfet_g5v0d10v5_54DD5S_0/sky130_fd_pr__pfet_g5v0d10v5:0 vs. VLS_1v8to5V_D1_And_VoltSelector_1407WL AMUX[15]/VLS 1 Low1v8 High5V2/inv_g5D102/sky130 fd pr pfet g5v0d10v5M1: l circuit1: 0.6 circuit2: 0.5 (delta=18.2%, cutoff=1%) VLS_16x2_1808_layout_WIRE_EXT_0//VLS_16x2_1708_layout_1//VLS_1x2_1708_layout_0[0]//VLS_1v8to5V_D1_And_VoltSelector_1407_layout_1//VLS_g5D10_LV1v8_HV5V_1//inverter_D1_g5v10_0//sky130_fd_pr__pfet_g5v0d10v5_54DD5S_0/sky130_fd_pr__pfet_g5v0d10v5:0 vs. VLS_1v8to5V_D1_And_VoltSelector_1407WL AMUX[14]/VLS 1 Low1v8 High5V2/inv_g5D102/sky130 fd pr pfet g5v0d10v5M1: l circuit1: 0.6 circuit2: 0.5 (delta=18.2%, cutoff=1%)

This looks like it is probably a real error in which there are two devices that have length 0.6um in the layout but 0.5um in the schematic.

Let me recheck this. Thanks

If you want to make sure that nets are not "virtually" connected through labels with the same name, then do

extract unique

before doing

extract all

. Then if there are power supplies that are not properly connected then they will show up as errors. For the user project wrapper, though, you may want to keep the existing behavior, as long as you know that the "unconnected nodes" are, say, pins around the wrapper edge that are not being used, which would be a non-issue.

This looks good option. But anyway to check open pins ( unconnected sublevel pins ?)

LVS would detect open pins below or on the top level, although

extract unique

will prevent missing opens that have both sides of the open labeled with the same name. For the warnings above, there are only 8 of them and you can check the reported positions to make sure that they are not issues.

@Tim Edwards @Mitch Bailey for the property errors - i have two types of issue - one is L mismatch for the inverter which i got the reason. But for the W mismatch im not sure why its flagging -- x1T1R_16x16_W7_RRAM_W0p5_16_08_layout1T1R 16x16 W7 RRAM W0p5 16 08 layout 0/x1T1R 1x16 W7 RRAM W0p5 16 08 layout1T1R_1x16_W7_RRAM_W0p5_16_08_layout_0[0]/x1T1R_W7_RRAM_W0p5_16_08_layout1T1R W7 RRAM W0p5 16 08 layout 0[14]//sky130 fd pr nfet g5v0d10v5 Y5YTSN 0/sky130 fd pr nfet g5v0d10v50 vs. 1T1R_16x16_W7u_xschem_RRAM_DEVICE_16081/1T1R 16x1 W7u xschem RRAM DEVICE 1608rram_column[0]/1T1R_W7u_xschem_RRAM_DEVICE_1608rram[0]/sky130 fd pr nfet g5v0d10v5M1: w circuit1: 49 circuit2: 7 (delta=150%, cutoff=7%) Result: Cells failed matching, or top level cell failed pin matching. So i have 7um nmos width with 7 fingers. How does the tool infer 7*7 = 49 width in this case ? Did i make a wrong connection

@Ryan R: I'm really not sure about that one. I've seen that happen when multiple instances were accidentally dropped on top of each other, but that's my only guess without looking at the layout.

Your

magic.spice

has 7 of these in parallel (

W=7

L=0.5

) x 7.

X4 a_524_n700# a_424_n726# a_366_n700# VSUBS sky130_fd_pr__nfet_g5v0d10v5 ad=2.03e+12p pd=1.458e+07u as=0p ps=0u w=7e+06u l=500000u

Your

xschem.spice

has 1

XM1 net1 WL SL VSS sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=7 nf=7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'

The

nf

parameter in

xschem.spice

does not effect L or W. It is only used to calculate

ad

and

as

. If the L parameters are equal, parallel mosfets are combined by summing the W parameters. So your layout is equivalent to a W=49 L=0.5 mosfet. Each layout should have W=1 to be equivalent to the schematic.

@Mitch Bailey - just to confirm : so for the schematic its fine correct ? Total 7um width with num fingers=7. Only i need to correct the layout.

Normally, you've done simulations on your schematic and want to create the layout with the same parameters. So yes, I suggest changing the layout.