Hello everybody. I'm making a 10 bit SAR ADC with merged switching scheme. My SAR doesn't behave as I would expect. In waveform dacp_dacn two conversions are shown. The first one looks good. The second one does something weird (marked with the green line at the top of the picture). From cycle 6 both the dacp and dacn start to rise in voltage. Instead of converging they start to diverg. When I check the other signals everything looks likes it behaves as it should. The clock signals act as expected and the bottom plates of the capacitors also charge correctly. This simualtion is run over the tt corner. Somebody has any idea what the origin of this problem can be? in attachment also .out .raw .spice .sch files Have a nice day kind regards

I had the same problem with pseudo resistors. If your transistors doesn't have any source and drain region areas set in the netlist, it may lead to those kind of convergence problems. Try to make the switches in layout and extract using the ext2spice -d option