open-source-silicon.dev

I am currently working on creating the GDS of an SoC, but I am facing an issue with the *Dbus_interconnect* module. This module has around 378 IOs, and although the logic is quite simple, I am restricted to an area of *200μm x 200μm*. How can I solve this problem, any suggestions?

The area is not the constraint here. And if you list all the 378 pins in the pin_order.txt file, openlane will create the GDS. After that see the total area of the GDS. if it is more than 200x200squm then try to see if the logic can be reduced. Then see how many IOs are allowed for packaging. For example tiny tapeout allow 26 IOs. Efabless allow 38 IOs.

Some time serial entry of data may reduce the pin count. 378 IOs can be fed with data by 38 package pins serially over multiple clock cycles. For that you need some extra registers or buffers. In a fancy way you can have a SPI protocol (or similar) to get data from pins and deserialize for 378 pins.  SERDES kind of concept.