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hi <@U01819B63HP> and <@U6GN0N3TM>,
working with the `nvt` MOS, magic extracts a strange netlist:
```XXM1 Vinput VSUBS Vinput sky130_fd_pr__nfet_03v3_nvt_7DHE2Q```
with only three pins available - I guess that would make sense since this is what the symbol looks like (screenshot attached).
However, it seems that these are kind of scrambled... By extracting differently connected device, it would seem that the first and third pins are drain and gate. However... the middle one seems to be the bulk and... there, apparently, is no source connector - even though it is available inside the subcircuit:
```.subckt sky130_fd_pr__nfet_03v3_nvt_7DHE2Q a_50_n100# a_n242_n322# a_n50_n188#
X0 a_50_n100# a_n50_n188# a_n108_n100# a_n242_n322# sky130_fd_pr__nfet_03v3_nvt ad=0.29 pd=2.58 as=0.29 ps=2.58 w=1 l=0.5
.ends```
The extracted netlist was obtained from Magic by:
```extract all
ext2spice lvs
ext2spice```
Can you please help me reach the source pin of this device?
Thanks

`sky130_fd_pr__nfet_03v3_nvt_7DHE2Q` is not a primitive that's just an extracted hierarchy level so the pins order will be random.

`sky130_fd_pr__nfet_03v3_nvt` is the primitive and it has 4 terminals as you can see.

ok, cool, thanks <@U016HU5HK8V>. But why doesn't it show source pin?

I'm guessing you have the source connected to the same signal as the bulk so it didn't expose them as separate pins ...

No, actually, source goes to another transistor, whereas bulk is connected to GND

<@U01E6DQR9KL>:  I have not been adding ports/pins to the generated cells in magic (which is something I need to do), so magic will only extract ports for nets in a subcircuit that are being connected to from outside the cell.  In your posted circuit, the source or drain connection `a_n108_n100#` does not appear as a port to the subcircuit, so magic believes it is not connected to anything outside the cell.  Maybe your are missing a contact in the layout?

Yes, that worked, thanks <@U016HU5HK8V> and <@U6GN0N3TM>