I am new to chip designing and currently learning different steps of ASIC design flow. I know that we run LVS to compare the netlists of layout and schematic. But I am not sure to what extent should we compare the two. Should we use LVS only to make sure whether layout and schematic have same circuits, nets and pins ? Or should we go ahead and also fix other warnings that come up after running LVS ? If so, does anyone have an idea how to fix these property errors ?

@Shavika Rastogi can you share the command you use to run LVS when posting results?

@Mitch Bailey Please see the previous thread. I have posted the command I used to run LVS.