Hi! I am trying to add a standard cell DFF in openlane by cell name: sky130_fd_sc_ms__dlrtp_1, but I get this error.

[INFO]: Using configuration in '../home/vboxuser/Documents/GitHub/samj-user-project/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /home/vboxuser/Documents/GitHub/samj-user-project/dependencies/pdks
[INFO]: Process Design Kit: sky130A
[ERROR]: Standard Cell Library 'sky130_fd_sc_ms' not found in PDK.
make[1]: *** [Makefile:80: user_proj_example] Error 255
make[1]: Leaving directory '/home/vboxuser/Documents/GitHub/samj-user-project/openlane'
make: *** [Makefile:126: user_proj_example] Error 2

user_proj_example.v

`default_nettype none

module user_proj_example (
`ifdef USE_POWER_PINS
    inout wire vccd1,    // User area 1 1.8V supply
    inout wire vssd1,    // User area 1 digital ground
`endif

    // Wishbone clock input
    input wire wb_clk_i,

    // Logic Analyzer Signals
    input wire la_data_in,   // Single bit input
    output wire [127:0] la_data_out  // 128-bit output, but we only drive the first 2 bits
);

    reg la_data_in_delayed_0;  // Register for introducing delay

    // Introduce delay on la_data_in using an always block
    always @(posedge wb_clk_i) begin
        la_data_in_delayed_0 <= la_data_in;  // Delay la_data_in by one clock cycle
    end

    /*tiny_test counter(
        .clk(wb_clk_i),      // Use wb_clk_i as the clock signal
        .rst(1'b0),          // Hardwire reset to 0 if you don't need a reset signal
        .d(la_data_in_delayed),      // Input data is la_data_in
        .q(la_data_out[0]),  // Output q
        .qb(la_data_out[1])  // Output qb
    );*/
    
    sky130_fd_sc_ms__dlrtp_1 u_sky130_fd_sc_ms__dlrtp_1 (
    .D(la_data_in_delayed_0),  // Data input
    .Q(la_data_out[0]),        // True output
    .Q_N(la_data_out[1]),      // Complementary output
    .RESET_B(1'b1),            // Reset is inactive (1'b1 for no reset)
    .GATE(wb_clk_i)            // Gating signal, often connected to the clock
    );

    // Set remaining bits of la_data_out to high impedance to avoid shorts
    assign la_data_out[127:2] = {126{1'bz}};

endmodule
`default_nettype wire

config.json

{
  "DESIGN_NAME": "user_proj_example",
  "DESIGN_IS_CORE": 0,
  "STD_CELL_LIBRARY": "sky130_fd_sc_ms",
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "dir::../../verilog/rtl/user_proj_example.v"
  ],
  "CLOCK_PERIOD": 25,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "counter.clk",
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 2800 880",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "MAX_TRANSITION_CONSTRAINT": 1,
  "MAX_FANOUT_CONSTRAINT": 16,
  "PL_TARGET_DENSITY": 0.55,
  "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
  "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
  "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
  "MAGIC_DEF_LABELS": 0,
  "SYNTH_BUFFERING": 0,
  "RUN_HEURISTIC_DIODE_INSERTION": 1,
  "HEURISTIC_ANTENNA_THRESHOLD": 110,
  "GRT_REPAIR_ANTENNAS": 1,
  "VDD_NETS": [
    "vccd1"
  ],
  "GND_NETS": [
    "vssd1"
  ],
  "IO_SYNC": 0,
  "BASE_SDC_FILE": "dir::base_user_proj_example.sdc",
  "RUN_CVC": 1,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "PL_TARGET_DENSITY": 0.45
  }
}

Is there any other way to add STD CELL LIBRARY.

@samarth jain volare installs the most common libraries by default. To install other libraries, try

volare enable -l <library>

If you are using the default

PDK_ROOT

and

PDK

, you may need to specify those on the command line. See

volare help

@Mitch Bailey Thanks for the reply! I managed to install it, but the make still uses hd library, and even after changing the config.json the ms libraries arent available to the flow. How can I "include" that library? Appreciate the help!

1. Check that the newly installed pdk is available

ls dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_ms

2. The config.json file has 2 entries for

"pdk::sky130*":

. I think you can remove the second shorter one.

Hi! I was texting from @samarth jain's acc. So ls reveals a subdirectory with various folders, looks normal. And I removed the shorter one. Edit: Sorry was looking in the wrong workspace, will try the correct one now.

I think that might be exactly the reason, although I’m surprised that it doesn’t default to the same. Can you try setting

STD_CELL_LIBRARY_OPT

too? (Hopefully you won’t need to set

STD_CELL_LIBRARY_CDL

or

STD_CELL_LIBRARY_OPT_CDL

. You can check the final config at

openlane/<block>/runs/<timestamp>/config.tcl

)

Still having the same problem. The libraries are updating as I set them in the config.json; but still can't find the module. Tried with hd as well, same result. I checked the no_synth.cells and found the modules in there, is it possible to use those cells in the flow?

@Anubhav Mukherjee If the cells are listed in the

no_synth.cells

then there was some reason to prevent them from being used in synthesis. Sometimes they cause drc errors when placed next to other cells. Not sure what to do in your case.

I see. Thank you for the help!

STD_CELL_LIBRARY_OPT

is super buggy…

Yea, I couldn't even get it to look up the cell, so kind of lost on what to do. Even for hd libs it didn't work, I tried. At this point I am thinking maybe we cannot instantiate by cell name in user_proj_example.v