Hey everyone. Cause of the hold violations in sky water pdk, we were thinking of using two latches at two different clocks instead of flip flop. Something like this. Does someone know how to do that in the tool?

why not simulate the flip flop hold timing and update the .lib with some margin or some derating?

how much hold violations you're getting?

Place a couple of buffers between Q output and D inputs if there is no logic in between. Anyway if you have hold violations the clock tree is not balanced. Some FFs are getting clock edge before others . A well designed standard cell library should not have Hold violations even if 2 flip flops are connected back to back (assuming they have same clock). Clock tree synthesis is an essential step in the RTL-to-layout flow.