Hey everyone, I'm trying to run precheck and I am getting the following error. Not so sure how to fix it:

2024-11-07 03:45:48 - [ERROR] - ERROR OEB FAILED, stat=6, see /home/roliveira/Desktop/osiris_i/precheck_results/07_NOV_2024___03_21_11/logs/OEB_check.log
2024-11-07 03:45:48 - [WARNING] - {{OEB CHECK FAILED}} The design, user_project_wrapper, has OEB violations.

@Rafael Oliveira gpio 31 and 32 have a non-fixed signal on the corresponding

io_out

. For output signals, the corresponding

io_oeb

signal must be low. Currently, none of the

io_oeb

signals are connected to anything. I recommend tying unused

io_out

signals low and unused

io_oeb

signals high to avoid possible leaks due to floating signals into logic gates. gpio 31 has both

io_in

and

io_out

connections. Is this a bi-directional signal? If so, during output,

io_oeb

should be low and during input,

io_oeb

should be high. BTW,

oeb

stands for output enable bar, where the bar refers to an inverted signal, i.e. active low.

Hey @Mitch Bailey I finally understood how the

io_out

,

io_in

and

io_oeb

works. This issue was solved by setting in the verilog the

io_oeb

low for enabling outputs I needed in my design (io_out[11:10]) and

io_oeb

high for enabling inputs (io_in[9:5]). The following lines were added in the verilog of my block.

assign io_oeb[9:5] = 5'b11111;     //  I/O[9:5]
    assign io_oeb[11:10] = 2'b00;     //  I/O[11:10]

In the user_defines I set the hex code to be 13'h0402 for inputs and 13'1008 for outputs:

`define USER_CONFIG_GPIO_5_INIT  13'h0402
`define USER_CONFIG_GPIO_6_INIT  13'h0402
`define USER_CONFIG_GPIO_7_INIT  13'h0402
`define USER_CONFIG_GPIO_8_INIT  13'h0402
`define USER_CONFIG_GPIO_9_INIT  13'h0402
`define USER_CONFIG_GPIO_10_INIT 13'h1808
`define USER_CONFIG_GPIO_11_INIT 13'h1808

@Rafael Oliveira Great! Looks like gpio 5-21 are user modes so you’ll want to connect

io_out

and

io_oeb

to avoid any leaks caused by floating inputs. The

io_out

and

io_oeb

signals are buffered in the caravel_core level for gpio 0-5? so it’s probably a good idea to tie those too. The

io_out

signals to gpio 5 - 9 are unconnected, so that might result in some leak. The simplest solution, I think, is to tie off any unused

io_out

and

io_oeb

signals.

I do not think I understood what you mean @Mitch Bailey. My design is only using io_in[9:5] and io_out[11:10]. So I set in the user_defines.v the USER_CONFIG_GPIO_5-11_INIT accordellly with what I need (13'h0402 for inputs and 13'h1808 for outputs) and the other ones just used a randon value. But in the wrapper I am only connecting the bits I need from

io_in

,

io_out

and

io_oeb

to my logic works. As I show bellow:

/*--------------------------------------*/
/* User project is instantiated  here   */
/*--------------------------------------*/
osiris_i_wrapper mprj (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),	// User area 1 1.8V power
	.vssd1(vssd1),	// User area 1 digital ground
`endif

    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),

    // MGMT SoC Wishbone Slave

    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_dat_i(wbs_dat_i),

    // Logic Analyzer

    // IO Pads
    .io_in (io_in[9:5]),
    .io_out(io_out[11:10]),
    .io_oeb({io_oeb[11:5]})

    // IRQ
);

So inside my design I tie the

io_oeb

as follows, and use the inputs and outputs to connect my logic:

assign io_oeb[5:0] = 5'b11111;     //  I/O[9:5]
    assign io_oeb[7:6] = 2'b00;     //  I/O[11:10]

@Rafael Oliveira The simplest answer is yes, you should tie all

io_oeb

and

io_out

outputs either high or low even if they are not used. 1. Some of these signals are buffered in the

caravel_core

block. If you don’t connect them, there can be a leak through the inverters with floating inputs. 2. Any gpio configured in a

USER

mode could have a leak if

io_out

or

io_oeb

is not connected. Just to be clear, unconnected the unused signals will not cause a logic problem. Just unexpected current leaks.

All right, just to clarify once again: if I am not using some GPIOs I can configure them as

MGMT

and i'll be fine not tie

io_out

or

io_oeb

, because the management area will take care of that. However, if I configure it as

USER

in the

user_defines.v

I do need to tie them to not have leak, even if I'm not using it. Did I understood correctly?

@Rafael Oliveira That is exactly correct… for signals that are not buffered in the

caravel_core

/

caravan_core

blocks. The signals that are buffered should be tied no matter if they are

USER

or

MGMT

. The signals that are buffered are different between

caravel

and

caravan

.

io_out[6:0]

and

io_oeb[6:0]

for user projects that connect to

caravel_core

and

io_out[26,1:0]

and

io_oeb[0]

for projects that connect to

caravan_core

.

All right, I get it. I'll fix it in my design. Once again thank you very much for the support.