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Hey everyone, I'm trying to run precheck and I am getting the following errors: 2024-11-07 04:25:33...
# sky130
r
Hey everyone, I'm trying to run precheck and I am getting the following errors: 2024-11-07 042533 - [CRITICAL] - {{FAILURE}} 2 Check(s) Failed: ['OEB', 'LVS'] !!!
precheck.log
About the LVS, the LVS_check.log shows LVS clean, however SOFT check results not clean. The reports are attached.
LVS_check.lognowell.ext.logext.logsoft.reportsoft.log
My LVS config
lvs_config.json
v
is your local precheck LVS passed?
r
These results are for the local LVS.
v
@Mitch Bailey can you plz have a look into this LVS issue?
r
Final lines of my LVS_check.log report:
Copy code
Soft check result:
Final result: 
Netlists do not match.
Soft check problem: check the following files
/home/roliveira/Desktop/osiris_i/precheck_results/07_NOV_2024___03_21_11/logs/ext.log
/home/roliveira/Desktop/osiris_i/precheck_results/07_NOV_2024___03_21_11/logs/nowell.ext.log
/home/roliveira/Desktop/osiris_i/precheck_results/07_NOV_2024___03_21_11/logs/soft.log
/home/roliveira/Desktop/osiris_i/precheck_results/07_NOV_2024___03_21_11/outputs/reports/soft.report

LVS result:
Final result: 
Circuits match uniquely.
.
LVS Done.

CVC result:
CVC: Total:                 0

Runtime: 0:39:45 (hh:mm:ss)

WARNING: possible errors SOFT 3 LVS 0 CVC 0
m
@Rafael Oliveira LVS is passing. What you may have a problem with is the soft connection check. This check is for high resistance connections through psubstrate or nwell that aren’t caught with LVS.
Looking at the 
soft.report
the problem appears to be in the 
mem_byte
block. Then 
input9/VPWR
net does not appear to be connected by metal to 
vccd1
. It is probably connected through nwell. Can you verify this? If it does appear to be connected through metal, then you may need to tell LVS to flatten some cells to achieve the correct extraction results.
r
All right, I'll check it. If it is connect how do I tell LVS to flatten the cells? Is this some configuration variable? By "cells" you mean the mem_byte or every std cells in this block?
m
It’s kind of tricky. Can we discuss that if it’s an issue?
r
Looking into the design it seems this particular cell is connecting the input9/VPWR to the vccd1 correctly. The gate level netlist also shows it is connected.
m
@Rafael Oliveira It looks like you’re using openroad to locate the cell. This is great. Can I suggest, opening the final gds (which is what we use for LVS) and verifying that the metal1 here is actually connected to the top metal5 power rails.
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