https://open-source-silicon.dev logo
Join Slack
Powered by
Subject: Help with LVS Mismatch Errors in Full Add...
# analog-design
p
Subject: Help with LVS Mismatch Errors in Full Adder-based Thermometer-to-Binary Encoder Layout Hi all, I'm currently working on a thermometer-to-binary encoder design using 4 full adders in my layout. However, I'm encountering LVS mismatch errors when running the check between the schematic and the layout. Here’s a summary of my design: 1. Full Adder Arrangement: 2. I've arranged the 4 full adders in 2 rows and connected them using tap cells for power and ground distribution. 3. Tap Cell Connections: ◦ The VPB (power) of the tap cells is connected to the VPWR (power) of the full adders. ◦ The VNB (ground) of the tap cells is connected to the VGND (ground) of the full adders. 4. Power and Ground Routing: 5. To make a common VPWR and VGND, I’ve used Metal 1 to short all the VPWR and VGND signals across the full adders and tap cells. Despite this setup, the LVS check is giving me errors related to the power and ground connections. From my understanding, the issue might be due to the way the tap cells are being handled or how Metal 1 is shorting the power and ground rails. Questions: • Is there a potential issue with how I’ve connected the tap cells to the full adders’ VPWR and VGND? • Could Metal 1 shorts between power and ground be causing LVS to flag this design as incorrect? • Are there any specific LVS rule violations I should check regarding the tap cells and full adder connections? Any insights or suggestions on how to resolve this mismatch would be really helpful! Thanks in advance for your help!
comp.outt2b.schT2B_DRC_FULL.magt2b_magic.spicet2b.spice
r
You may want to have another look at the schematic, looking at the comp.out your schematic seems to be on the right hand side and shows the four 'power' nets while your layout only has two listed. Did you edit the properties of the standard cell symbols in your schematic to connect the substrate connections to the right nets?
This is the relevant part of the comp.out file, you can see that the layout (on the left) has fewer nets than the schematic and it gives a list of which nets didn't match:
Copy code
Subcircuit summary:

Circuit 1: t2b_magic                       |Circuit 2: t2b                             
-------------------------------------------|-------------------------------------------
sky130_fd_pr__nfet_01v8 (56)               |sky130_fd_pr__nfet_01v8 (56)               
sky130_fd_pr__pfet_01v8_hvt (56)           |sky130_fd_pr__pfet_01v8_hvt (56)           
Number of devices: 112                     |Number of devices: 112                     
Number of nets: 65 **Mismatch**            |Number of nets: 67 **Mismatch**            
---------------------------------------------------------------------------------------
NET mismatches: Class fragments follow (with fanout counts):

Circuit 1: t2b_magic                       |Circuit 2: t2b                             
---------------------------------------------------------------------------------------
Net: sky130_fd_sc_hd__fa_1_0.VNB           |Net: VGND                                  
  sky130_fd_pr__nfet_01v8/(1|3) = 36       |  sky130_fd_pr__nfet_01v8/(1|3) = 36       
  sky130_fd_pr__nfet_01v8/4 = 56           |                                           
                                           |                                           
Net: vpwr                                  |Net: VPWR                                  
  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 36   |  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 36   
  sky130_fd_pr__pfet_01v8_hvt/4 = 56       |                                           
                                           |                                           
(no matching net)                          |Net: VNB                                   
                                           |  sky130_fd_pr__nfet_01v8/4 = 56           
                                           |                                           
(no matching net)                          |Net: VPB                                   
                                           |  sky130_fd_pr__pfet_01v8_hvt/4 = 56       
---------------------------------------------------------------------------------------
Netlists do not match.
p
This is how, my properties of standard cell looks.. like.. is this the way, it should look..?
this is my layout.. of t2b
r
the four parameters VNB, VPB, VGND, and VPWR tell where the substrate and power connections go, now they are all connected to individual nets which is probably not what you want. You can connect the nwell (p-transistor substrate) to the power by making VPB=VPWR for example. Or connect the pins to named nets if you want to use other names for your power nets (e.g. VPB=VDD VPWR=VDD VNB=GND VGND=GND)
For the layout, you can flip the top row upside down and overlap the power rails of both rows. This is typically done in standard cell designs for a more compact design. Also, it's good practice to use m1 for horizontal wires only, and m2 for vertical wires. This will save you some trouble from routing collisions if you get into more complex designs.
👍 1
(F in magic flips things upsidedown)
p
@Roel Jordans Thankyou so much.. I will do the changes and inform you sir.. thanks again,,
lvs matched sir...
👍 2
7 Views
Open in Slack
PreviousNext
Powered by