open-source-silicon.dev

`netgen` can't parse `assign mux_ref = addr[11:2];` ? Is that expected ?

Well, I do occasionally run into syntax that doesn't parse the way I expect it to.  Netgen does not have a complete verilog parser, which would be a pain to write.  The statement above is pretty straightforward.  I don't think it's the syntax specifically but more likely that netgen has decided that `mux_ref` is not a vector, or at least not a 10-bit vector, and can't do the mapping.  If you send me an example I can figure out where netgen's parser got confused.

lvs.zip

Everything in the verilog looks perfectly normal.  I'll take a look at why netgen is having problems with it.

<@U016HU5HK8V>:  Sorry for taking over a week to get to this, but I found the error, which was a matter of calling the wrong routine to parse out a bus delimiter, and occurs for cases of "assign vector1 = subvector2[a:b]" and also "assign subvector1[a:b] = vector2".  It is now fixed in netgen version 1.5.287 (along with merging your pull request from an absurdly long time ago).  The update is in the git repository on <http://opencircuitdesign.com|opencircuitdesign.com> and will get copied to the github mirror in about 6 hours.  I apologize especially as the week in which I didn't get around to looking at it included the November shuttle run tapeout date (which is not a coincidence---I'm just starting to work through my backlog of issues).

<@U016EM8L91B> Thanks for the fixes. And no worries for the delay, I had viable workaround for both so this wasn't blocking for tapeout.  I know the shuttle tapeout dates tend to be very busy times !