Hello everyone, I recently hardened several macros in my design, allowing up to metal layer 5 (met5) for routing and using vertical met4 stripes for the power connection. Afterward, I integrated these macros into a top module and added a power ring using met4 and met5 layers. This top module was then integrated into the

user_project_wrapper

. I'm wondering if this approach might present any issues because I am using a ring with met5 and mt4 in my topmodule. Specifically, I encountered a situation where I had to set

"RUN_IRDROP_REPORT": false

to avoid the following warning when integrating my top module in the user_project_wrapper: >

[WARNING PSM-0038] Unconnected PDN node on net vccd1 at location (1426.418um, 1542.240um).

Upon reviewing the design, I noticed that vias have been added to establish the necessary connections. Does anyone have insights or suggestions on addressing this approach is ok?

@Rafael Oliveira You can see at the top level that the horizontal met5 power rails appear in repeating groups of 8, while your top macro has evenly spaced horizontal power rails.

WB_BRIDGE

only intersects with one power rail which is probably a problem. Either reduce the pitch or move the macro so that it intersects with both a power and ground. The user_project_wrapper level appears to be ok with the top level horizontal power rails avoiding the macro met5.

The image of the WB_BRIDGE above wasn’t very clear. There are two power rails intersecting with the block—one for vccd1 and one for vssd1—as shown below:

@Rafael Oliveira Sorry for the false assumption. I can’t really tell from the screen shot, but are there 2 vertical met4 power rails over the standard cell rows to the right of

U_CORE

? You want check both the vssd1 and vccd1 connections. Are there 2 sets of vias at the error location? As for the last question, as long as the top level power rails can route over the top of the macro, I think you’re ok.