Hey everyone, I'm working on a design that include...
# sky130
r
Hey everyone, I'm working on a design that includes three sub-blocks. I've hardened each of these sub-blocks and I am now in the process of instantiating them in the top module. However, I’m encountering an issue at stage 7, specifically during the PDN generation. If setting these two variables to false allows the flow to complete successfully, it’s likely that these checks are causing interruptions or additional verifications that could be failing or adding constraints. "FP_PDN_CHECK_NODES": false, "RUN_IRDROP_REPORT": false However, disabling checks can potentially skip over important validations, which may impact the robustness or correctness of the design. I attached my config.json
m
Are the power pins in the macros
vssd1
and
vccd1
or
VPWR
and
VGND
?
r
In the verilog I set for each macro to be: `ifdef USE_POWER_PINS inout vccd1, inout vssd1, `endif and in the config.json for each macro I set: "VDD_NETS": "vccd1", "GND_NETS": "vssd1", "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS"
v
If LVS pass then good to go
👍 1
r
I have found this https://openlane2.readthedocs.io/en/latest/usage/pdn.html about the FP_PDN_CHECK_NODES, so it seems ok set it to false.
But now, when I reach step 35 I get the following error. My config.json now is: "FP_PDN_CHECK_NODES": false, "RUN_IRDROP_REPORT": true
m
@Rafael Oliveira It appears that the power rails are not connected to the hard macros. There could be many reasons - macro height, macro power rail placement, etc. As to why that is, we probably need to look at your actual data - the verilog files, the hard macro gds and lef files, the intermediate odb files, etc. Can you share your repo?
r
Based on the GDS file, the rails appear to be correctly connected to the macros. Here is the repository and branch I’m currently working on: https://github.com/grouposiris/osiris_i/tree/pnr
Is there any issue with hardening macros using the following settings?
Copy code
"FP_PDN_MULTILAYER": true,
"FP_PDN_CORE_RING": true
These settings create a ring around the macros using metal layers 4 and 5. I'm uncertain whether this could cause issues when integrating the macro into the
caravel_project_wrapper
.
m
Take a look at the macro lef files to verify that the top level metal5 can connect with the vertical metal4 power ring on the macro.
r
Yes, loking into the GDS I see that the vias has been created correctly and the top level met5 is connecting with the vertical met4 strip, even though the Unconnected error is showing.
m
See response in other thread.