Hello everyone, I've designed a 10-bit fully diff...
# analog-design
r
Hello everyone, I've designed a 10-bit fully differential SAR ADC, and I’d like to share the results with you. However, the FFT analysis for 64 points in Cadence didn’t meet my expectations—I’m only achieving 3.4 bits of resolution, which is significantly below the target of 10 bits. Any suggestions on what might be causing this discrepancy? Could I be overlooking something? Tsampling=13 uS , fin=(7/64)*(1/13 uS), Tsimulation=(64**13 uS)+13 uS=845 uS Thank you!
m
64-points is too less, for 10bit take at least 2^10 points
r
I did another simulation with 512 points and it increased to 4.7 bits.
a
Even looking at your time domain that looks much less than 10bit. It looks like there is only a handful of levels. Is your simulation tilmestep too high?
m
Do not give full scale in the beginning
r
I used high performance simulation mode. That may cause the problem.
I gave half of full scale, but the result was the same.
a
by high performance do you mean aps? this should be okay at 10bit. but will need to set to conservative accuracy. assuming you are using spectre
r
Yes I used aps with conservative accuracy
a
I would do a very slow sine wave or a dc sweep of the input to see if you get all the codes. But this isn't just an FFT setting as the time domain is definitely showing something around 3-4 bits.
Maybe your bandwidth is much less than fs/2?
r
The input signal is 8 kHz and sampling clock is around 79 kHz. They are quite slow signals. I will do the ramp test to see how it’s work. Thank you @Alex Sheldon
x
test INL and DNL using the ramp signal first.