open-source-silicon.dev

Mmm, I think `write_cdl` is giving me a different netlist than `write_verilog` ...

Well, some of the top level ports are just plain just not connected in the CDL :sweat_smile:

tt_mux.cdl

tt_mux.pnl.v

<@U016HU5HK8V> `um_iw` is not connected in either netlist as far as I can see.

`assign um_iw[10] = \block[0].zbuf_iw_I[10].z ;`
```  sg13g2_and2_2 \block[0].zbuf_iw_I[10].genblk1.cell0_I  (.A(\block[0].zbuf_iw_I[10].a ),
    .B(\block[0].l_ena_0_I.z ), 
    .X(\block[0].zbuf_iw_I[10].z ),
    .VDD(VPWR),
    .VSS(VGND));```

<@U016HU5HK8V> Sorry, the browser window I was using didn’t hit any of the assigns on a search. Scrolling down to the bottom of the file there are definitely assign statements with `um_iw`.

Maybe `write_cdl` doesn’t handle assigns.

The source is an openroad db and the connection in there is definitely good.

I'll try and read how `write_cdl` works after I eat and see if I can see anything wrong in there ...

Definitely a bug. `write_cdl` doesn't account at all for pins that are connected to nets with a different name ...

Calibre CDL allows a `*.connect` statement to join nets. Don’t know if that’s standard spice or not. If LVS understands it, then that might be a solution.

I just modified it to use the pin name instead of the net name in those cases.