Hi, I have some questions about Caravel mprj_io pads and user_clock2. My project needs 8 IO pads, and the RTL uses

io_out[7:0]

for this (along with setting

io_oeb[7:0]

to low). Is there anything wrong with this? My design is a simple 8-bit CPU, and I plan to load its 16 bytes of RAM using logic analyzer inputs with a faster clock, and then switch to a slower clock, enable the CPU and view what it's doing through the 8 IO pins (connected to the CPU "output" register). I know that

user_clock2

initially has the same frequency as the wishbone/cpu clock, but I don't have experience with DLLs/PLLs so I'm not sure how slow I can make it go.

@Sameer Srivastava the gpio default configurations for gpio 0-4 are fixed as MGMT driven. In order to use them for user output, you will also need to run a firmware program to reprogram the defaults. If you wanted to avoid this, you could use

io_out[12:5]

and tie

io_oeb[12:5]

low. These gpio defaults are user configurable with

verilog/rtl/user_defines.v

.

To clarify, GPIO 0-6 have useful functions for the management processor (housekeeping SPI and UART) and so using GPIO 0-6 for user project signals interferes with basic processor functions and requires extra effort to test. Unless you really need more than 31 GPIO signals, then keep things simple and use GPIO 7 and higher. Do not use

user_clock2

unless it is for something that is completely uncorrelated to the processor/wishbone clock, or else you will have synchronization issues unless you really know what you're doing with multiple clock domains. If you want a slow clock, then input a clock from off-chip through a GPIO or else implement a counter and divide the core clock down to the frequency you need.

Thanks! I have implemented a counter that counts to 16,666,666 and toggles a

slowclk

reg to get a roughly 3 Hz clock from the 50MHz clock.