See above ... without being declared a sub circuit, it doesn't have any pins because you haven't defined any, hence it didn't check anything ...

@tnt Do we need to uncomment the ".subckt" and ".ends" statement in both netlists (generated from xschem and magic) ?

They're not commented in the one generated from magic.

@Shavika Rastogi As @tnt says, if the top level subckts in both netlists do not have the same name, you’ll have to specify what you want to compare. Try this

netgen -batch lvs "ota_lvs.spice OTA" "gm_mos_bias.spice gm_mos_bias" ~/foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl

@Mitch Bailey Thank you so much for your suggestion. It works ! However, the netlists generated from schematic and layout do not match. I am trying to find out what went wrong. Here is the comp.out file that was generated after running lvs :

@Shavika Rastogi looks like the setup file may not be referenced. Can you share the actual netgen command you used and the screen output? The denominators are the pin numbers. For mosfets

2

is the gate and

4

is the bulk connection. Since mosfet source/drain should be interchangeable, those terminals should show up as

(1|3)

but they do not.

Here is my layout :

Your netgen may be out of date. I’m using

1.5.276

. Looks like your on

1.5.240

. This may not be a major problem, though. Is that the right path to the setup file?

I am using the docker container by efabless. The setup files (with extension .tcl) for sky130A are located in the path /foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl

I find it easier to debug LVS results if the layout and schematic have exactly the same net names including case. Also helps if the layout and schematic cell names are the same.

I can make the layout and schematic cell names same by renaming them. But how to make the net names of layout and schematic same ?

just the ports is usually sufficient.

Do you mean ports of layout (vdd,vss,plus,minus,bias, out) and schematic (VP, VN, PLUS, MINUS, BIAS, OUT) should be same ?

yes.