Does executing a single

lw zero,(zero)

instruction in place of the NOP single or multiple instructions change anything? I believe there is a MMIO wishbone write-back starving bug that is in the litex Vex arbiter, while the cpu has separated I and D paths the litex adapter merges them into one to access wishbone for data, io and xip functionality. The LW R0 style nop forces the CPU to stall if there is a dirty store still outstanding this forces the arbiter to release instruction fetch priority allowing the write to occur