Hi, LVS check in precheck step for my design using caravel_user_project is taking a very long amount of time (~3 hours now for a very simple design). What could be the issue? OpenLane flow runs successfully and I have my gds files updatded in the repo. I am following unic-cass.github.io/training/4.5-integrate-your-design.html . Maybe I need to reduce my project area?

do you have data pushed into github repo to analyze? Just kill it and re-run again otherwise. Precheck depends on design complexity

The flow completed successfully and I did push the updated files (gds and others) to the repo.

run

htop

and check run status in another terminal

I see netgenexec consuming 99% cpu

it means LVS running currently

Yeah it just failed.

@Sameer Srivastava

disconnected nodes

are probably not a problem. That just means there are pins that are not connected to any devices. These messages, on the other hand, are something to be concerned about.

Flattening instances of sky130_ef_sc_hd__decap_12 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_ef_sc_hd__decap_12 in cell user_proj_example (1) makes a better match
Flattening instances of sky130_fd_sc_hd__a2bb2o_1 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_fd_sc_hd__o21a_1 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_fd_sc_hd__o21a_1 in cell user_proj_example (1) makes a better match
Flattening instances of sky130_fd_sc_hd__and2_1 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_fd_sc_hd__and2_1 in cell user_proj_example (1) makes a better match
Flattening instances of sky130_fd_sc_hd__clkinv_16 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_fd_sc_hd__conb_1 in cell user_proj_example (0) makes a better match
Flattening instances of sky130_fd_sc_hd__conb_1 in cell user_proj_example (1) makes a better match
...

This only happens when the cell counts don’t match between the layout and schematic. Are you running LVS in precheck or as part of the openlane flow?

@Marwan Abbas here is the discussion

This is from precheck. I also ran openlane on it (

make user_proj_example

) and the flow succeeded.

openlane’s lvs is uses abstracted cells. precheck’s lvs is full device level LVS. Can you share your

lvs.log

and

lvs.report

files? It’s ok if they are incomplete.

lvs.log - https://0x0.st/XlY-.log lvs.report - https://0x0.st/XlxP.report

The log file has these messages

Warning:  Net {io_oeb[37],io_oeb[36],io_oeb[35],io_oeb[34],io_oeb[33],io_oeb[32],io_oeb[31],io_oeb[30],io_oeb[7],io_oeb[6],io_oeb[5],io_oeb[4],io_oeb[3],io_oeb[2],io_oeb[1],io_oeb[0]} bus width (16) does not match port io_oeb bus width (8) or array width (1).
Warning:  Net {io_out[37],io_out[36],io_out[35],io_out[34],io_out[33],io_out[32],io_out[31],io_out[30],io_out[7],io_out[6],io_out[5],io_out[4],io_out[3],io_out[2],io_out[1],io_out[0]} bus width (16) does not match port io_out bus width (8) or array width (1).
Warning:  Net {la_data_in[127],la_data_in[126],la_data_in[125],la_data_in[124],la_data_in[123],la_data_in[122],la_data_in[121],la_data_in[120],la_data_in[119],la_data_in[118],la_data_in[117],la_data_in[116],la_data_in[115],la_data_in[114],la_data_in[113],la_data_in[112],la_data_in[111],la_data_in[110],la_data_in[109],la_data_in[108],la_data_in[107],la_data_in[106],la_data_in[105],la_data_in[104],la_data_in[103],la_data_in[102],la_data_in[101],la_data_in[100],la_data_in[99],la_data_in[98],la_data_in[97],la_data_in[96],la_data_in[95],la_data_in[94],la_data_in[93],la_data_in[92],la_data_in[91],la_data_in[90],la_data_in[89],la_data_in[88],la_data_in[87],la_data_in[86],la_data_in[85],la_data_in[84],la_data_in[83],la_data_in[82],la_data_in[81],la_data_in[80],la_data_in[79],la_data_in[78],la_data_in[77],la_data_in[76],la_data_in[75],la_data_in[74],la_data_in[73],la_data_in[72],la_data_in[71],la_data_in[70],la_data_in[69],la_data_in[68],la_data_in[67],la_data_in[66],la_data_in[65],la_data_in[64],la_data_in[63],la_data_in[62],la_data_in[61],la_data_in[60],la_data_in[59],la_data_in[58],la_data_in[57],la_data_in[56],la_data_in[55],la_data_in[54],la_data_in[53],la_data_in[52],la_data_in[51],la_data_in[50],la_data_in[49],la_data_in[48],la_data_in[47],la_data_in[46],la_data_in[45],la_data_in[44],la_data_in[43],la_data_in[42],la_data_in[41],la_data_in[40],la_data_in[39],la_data_in[38],la_data_in[37],la_data_in[36],la_data_in[35],la_data_in[34],la_data_in[33],la_data_in[32],la_data_in[31],la_data_in[30],la_data_in[29],la_data_in[28],la_data_in[27],la_data_in[26],la_data_in[25],la_data_in[24],la_data_in[23],la_data_in[22],la_data_in[21],la_data_in[20],la_data_in[19],la_data_in[18],la_data_in[17],la_data_in[16],la_data_in[15],la_data_in[14],la_data_in[13],la_data_in[12],la_data_in[11],la_data_in[10],la_data_in[9],la_data_in[8],la_data_in[7],la_data_in[6],la_data_in[5],la_data_in[4],la_data_in[3],la_data_in[2],la_data_in[1],la_data_in[0]} bus width (128) does not match port la_data_in bus width (14) or array width (1).
Error:  Instance mprj has pin wb_rst_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_ack_o which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_cyc_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_stb_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_we_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin io_in which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin irq which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin la_data_out which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin la_oenb which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_adr_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_dat_i which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_dat_o which is not in the user_proj_example cell definition.
Error:  Instance mprj has pin wbs_sel_i which is not in the user_proj_example cell definition.

Does does the verilog lint check before synthesis flag any problems?

I don't have those logs, but yes it does complain about those vectors being trimmed. I instantiated user_proj_example in user_project_wrapper and removed everything but

la_in

,

wb_clk_i

,

io_out

and

io_oeb

, and passed in slices of those from the declaration of

user_project_wrapper

. Am I also supposed to remove the pins I don't need from somewhere else except from user_proj_example.v and user_project_wrapper.v ?

You’ll need to keep all the

user_project_wrapper

pins. However, in the instantiation of

user_proj_example

in

user_project_wrapper

, only connect the ports with the bus widths that actually exist in the

user_proj_example

gate level verilog.

I think I have done exactly this. All pins in the definition of

user_project_wrapper

are there. In the instantiation of

user_proj_example

, I have connected only the pins I need with proper bus widths (also edited the definition of

user_proj_example

to match these widths).

@Sameer Srivastava I see your user_proj_example.v.

module user_proj_example (
`ifdef USE_POWER_PINS
    inout vccd1,	// User area 1 1.8V supply
    inout vssd1,	// User area 1 digital ground
`endif
 
    // Wishbone Slave ports (WB MI A)
    input         wb_clk_i,
    //input         wb_rst_i,
 
    // Logic Analyzer Signals
    input  [13:0] la_data_in,
    //output [127:0] la_data_out,
    //input  [127:0] la_oenb,
 
    // IOs
    //input  [BITS-1:0] io_in,
    output [7:0] io_out,
    output [7:0] io_oeb
 
    // IRQ
    //output [2:0] irq
);

You should not leave or comment out un-used port during hardening. It will create an issue during wrapper level.

So I keep all of these there, even in user_proj_example (and not handle those I don't need in my logic), but while instantiating it I just connect the relevant ports with widths that I need?

Yes use IO which you need to connect, leave the remaining, its automatically tied to constant during hardening. In wrapper just instantiate module and run. So you will not face hold violations and LVS issue.

I see. Will make these changes and run the flow and precheck again.

@Anton Maurovic (efabless support) fyi

Thanks for all the help! I finally got clean LVS and a passing precheck.

Great to hear @Sameer Srivastava. Do you have any outstanding issues at this point, or anything else you need help with?

@Anton Maurovic (efabless support) no outstanding issues right now. Thanks!