Hello, I was working on the mixed signal design (3-bit flash ADC) and I bit confused with the flow....actually I generated a synthesised netlist of a 8 x 3 encoder using yosys with the

sky130_fd_sc_hd

library, I want to know how can we use this encoder as a block in my ADC schematic in xschem ? Do I need to convert the

.v

to a

spice

file and manually connect my encoder with the other blocks ? If I am not wrong if I can get

spice

file from the

.v

then I can get the schematic in the xschem.....🤔

You need to create just a xschem symbol wiith the same I/O ports as your synthetized block. Then include the spice netlist of the block. see this manual page, in particular the section:

4. Obtaining the pin ordering from the subcircuit definition specified via spice_sym_def

Thanks for the reply @Stefan Schippers, but here you can see my synthesised netlist is in verilog format will this works in xschem ?

/* Generated by Yosys 0.9 (git sha1 1979e0b) */

(* top =  1  *)

(* src = "prio_enc.v:14" *)

module P_encoder(in, Out);

wire _00_;

wire _01_;

wire _02_;

wire _03_;

wire _04_;

wire _05_;

wire _06_;

(* src = "prio_enc.v:17" *)

output [2:0] Out;

(* src = "prio_enc.v:16" *)

input [7:0] in;

sky130_fd_sc_hd__clkinv_1 _07_ (

.A(in[3]),

.Y(_00_)

);

sky130_fd_sc_hd__nand2b_1 _08_ (

.A_N(in[2]),

.B(in[1]),

.Y(_01_)

);

sky130_fd_sc_hd__a21oi_1 _09_ (

.A1(_00_),

.A2(_01_),

.B1(in[4]),

.Y(_02_)

);

sky130_fd_sc_hd__nor2_1 _10_ (

.A(in[5]),

.B(_02_),

.Y(_03_)

);

sky130_fd_sc_hd__o21bai_1 _11_ (

.A1(in[6]),

.A2(_03_),

.B1_N(in[7]),

.Y(Out[0])

);

sky130_fd_sc_hd__nor2_1 _12_ (

.A(in[4]),

.B(in[5]),

.Y(_04_)

);

sky130_fd_sc_hd__o21ai_0 _13_ (

.A1(in[2]),

.A2(in[3]),

.B1(_04_),

.Y(_05_)

);

sky130_fd_sc_hd__nor2_1 _14_ (

.A(in[6]),

.B(in[7]),

.Y(_06_)

);

sky130_fd_sc_hd__nand2_1 _15_ (

.A(_05_),

.B(_06_),

.Y(Out[1])

);

sky130_fd_sc_hd__nand2_1 _16_ (

.A(_04_),

.B(_06_),

.Y(Out[2])

);

endmodule

I've also had some success in the past using the scripts found in the xschem part of the PDK at

$PDK_ROOT/$PDK/libs.tech/xschem/xschem_verilog_import

@Sudeep Gopavaram You need to save a spice netlist from the synthetized design. I think yosys can do that directly.

@Sudeep Gopavaram: I'm at the same point as you so very interested here. Not sure if any of the attached will help but the doc details how I got a verilog file (4b counter) to run in xschem. The .txt file contains the commands I used to get Yosys to synth it into a .v file. Since then I have got sidetracked with some openlane stuff but plan to come back to this. Please update if you have any progress. Basically, I want to run my synthesized netlist in xschem.