Hello everyone. We have a project needing to know the breakdown voltage of the gate of NMOS or in other words NMOS Characterization therefore grounding the drain and source gates. But it's giving me a weird graph. We tried changing the igcmod = 2, igbmod = 1 , nigbinv = 3.0, nigbacc = 1.0, and nigc = 1.0 The first photo is the output without changing anything in BSIM 4.5. The second photo is the one with changes. Is there anything wrong with the way I'm simulating it? Also, is there another way to find the Gate Breakdown Voltage?

@John Praxie Alcanzo In other processes I have worked with the I/V charasteristic of gate oxide (breakdown / tunnel current) was not modelled at all. In general you have to stay well below the breakdown value. (something around 2.1 Volts for 1v8 transistors) to fulfit aging requirements. For sky130 I don't know if gate current is described (@Tim Edwards)

You should plot in the log scale. Maybe there are reasonable current values for gate voltages where the current seems flat.

@Luis Henrique Rodovalho I tried to simulate a LV (1.8V) fet with gate voltage ramped up to 15V. Gate current is zero, it can not be plotted on a log scale. By inspecting the data file:

Index   v-sweep         i(vg)           
--------------------------------------------------------------------------------
...
1447    1.447000e+01    0.000000e+00
1448    1.448000e+01    0.000000e+00
1449    1.449000e+01    0.000000e+00
1450    1.450000e+01    0.000000e+00
1451    1.451000e+01    0.000000e+00
...

At 15V a 1.8V tiny oxide should turn to a low resistance antifuse and destroy the transistor. This effect is however not described by the spice model.

@Stefan Schippers it seems @John Praxie Alcanzo modified some of the transistors parameters so it could output something. Ngspice should be able to handle it. Maybe someone from the community has taped out a chip for transistor characterization and could measure breakdown voltages that aren't modeled and update it. It is not an easy task but is doable.

Just adding that I have not seen this modeled in any commercial technology that I have worked with. Usually a series of empirical models (i.e. spreadsheets) are used in combination with checks/asserts in the simulator to see what devices are outside a safe area which is determined from destructive testing on a few sample wafers.

When we tried using Cadence Virtuoso with the same circuit using GPDK045 and this was the output. The output graph of NMO/G is what I'm trying to get using skywater130. We wanted to know the gate breakdown voltage for sky130pdk NMOS so that we can create a circuit controlling when the nmos' gate will break i.e antifuse.