When we run "make user_project_wrapper" this integrates our design into the user project area right? Don't we have to connect this with the management core after this step? Is it done by efabless?

user_project_wrapper

includes pins that connect to the management core and gpio cells. All you need to do is submit your

gds/user_project_wrapper.gds

and

verilog/rtl/user_defines.v

.