Arsath Jafar
10/15/2024, 11:53 AMAnton Maurovic (efabless support)
10/15/2024, 12:56 PMopenlane/user_project_wrapper/macro.cfg
and see what cells (macros) you have in there, then make sure there are Verilog module instances with those same names in verilog/rtl/user_project_wrapper.v
-- also, be sure you have run make YOUR_MACRO_NAME_HERE
for each module name you are using inside the user_project_wrapper
Verilog module. Finally, share your user_project_wrapper.v
file here. It's likely you have some logic in it which cannot be synthesized at the top level (for example: you have something like a small number of gates, or even a constant like 1'b0
which cannot be done at the top level, but there are ways this should be handled differently that we can help with).Vijayan Krishnan
10/15/2024, 1:25 PMArsath Jafar
10/16/2024, 5:28 AMAnton Maurovic (efabless support)
10/16/2024, 5:44 AMAnton Maurovic (efabless support)
10/16/2024, 5:44 AMAnton Maurovic (efabless support)
10/16/2024, 5:45 AMmake user_project_wrapper
. Line 94 is a problem because 2'b00
requires two "tie low" conb
cells.Anton Maurovic (efabless support)
10/16/2024, 5:45 AM~
)Anton Maurovic (efabless support)
10/16/2024, 5:47 AMassign user_irq[0] = user_sys_irq;
-- you don't need to assign the other 2 bits at all (so long as you keep the respective IRQs disabled in firmware, which is their default state anyway)Anton Maurovic (efabless support)
10/16/2024, 5:48 AMi3c_dut_top
) to generate those signals with the correct (inverted) polarity.Anton Maurovic (efabless support)
10/16/2024, 5:49 AMAnton Maurovic (efabless support)
10/16/2024, 5:52 AMi3c_dut_top
-- have you already run make i3c_dut_top
(and hence do you have it hardened as gds/i3c_dut_top.gds
? If not, you will need to run that make i3c_dut_top
also to generate your macro.Anton Maurovic (efabless support)
10/16/2024, 5:53 AMopenlane/user_project_wrapper/config.json
file and macro.cfg
from the same directory.Arsath Jafar
10/16/2024, 5:55 AMArsath Jafar
10/16/2024, 9:36 AMVijayan Krishnan
10/16/2024, 10:00 AMuser_project_wrapper.v
update following lines: i3c_dut_top i3c_master(
to i3c_dut_top mprj(
it will workArsath Jafar
10/16/2024, 10:56 AMArsath Jafar
10/16/2024, 10:59 AMVijayan Krishnan
10/16/2024, 11:17 AM20 20 N
, so no place for routing. Move macro position to 60 800 N
and try againAnton Maurovic (efabless support)
10/22/2024, 8:53 PMArsath Jafar
10/23/2024, 4:10 AM