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How does the klayout LVS deep mode find hierarchy ...
# klayout
t
How does the klayout LVS deep mode find hierarchy boundary ? I'm trying to run LVS on a iHP design and it's failing because it seems to extract the diodes from the 
sg13g2_antennanp
standard cell at the "top level" rather than in a sub cell and so it doesn't get matched to the CDL whihc has it as a subcell. Running LVS on the ``sg13g2_antennanp` itself (using it as the top cell) works. Using the flat mode also works ... so it's some kind of hierarchy problem but I don't see what's failing and why.
k
@Amro Tork @Farag Elsayed any comments on that ?
a
@tnt Hierarchy management in KLayout is kind of unexpected. We usually advise to run flat if possible. Or black box cells if you have large design. And make sure that that cells that are black boxed are LVS clean as well.
👍 1
t
I think the issue is related/similar to https://github.com/KLayout/klayout/issues/1813 but the fix doesn't see trivial to apply here.
I guess we can run it flat for now. This was for the "controller" and "mux" sub blocks. For the top level I want to black box and only check the first level wiring but I'm not even sure how to do that. 1. AFAICT this requires patching the LVS script so we have to copy and alter the script in the PDK, making it a pain for later update since we basically have to maintain a fork. Ideally we'd be able to include the whole extraction part from the PDK rather than have to copy it and maintain it in sync 2. I'm not even sure how that's supposed to work because AFAICT the extraction itself is run on the whole loaded GDS and then after extraction you can black box some of the subcells in both schematic and extracted layout so that they don't influence the comparaison. HOWEVER that doesn't help at all if the extraction steps gets confused and extracts some of the device (here the diodes) at the wrong level of the hierarchy ... I also tried playing with 
select
after reading the GDS but that's not good either because de-selecting the cell means it's not extracted at all rather than being extracted as an empty box ( you end up with no instance of it at all, meaning wires to/from it are not checked which is not good ).
a
@tnt Blackboxing at the layout level should affect the extraction step in LVS. You would need to add the following line in the LVS code you have: https://www.klayout.de/doc/manual/lvs_tweaks.html#h2-147 I know it's not convenient. But we could think of a possible enhancement down the line to make this GUI feature to black box cells. I didn't review your layout. Does your device has a layer that comes from a different cell to properly being recognized?
f
Related to issue mentioned above, I believe it was covered in the current LVS implementation https://github.com/KLayout/klayout/issues/1715
t
@Farag Elsayed mmm I guess this change doesn't work for the antenna cell ... it works for all others.
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@Amro Tork What do you mean by "blackboxing at the layout level" ?
Also, the layout is just standard cells I didn't add any special layers or manual drawings.
a
@tnt Check the link that I have sent. It should help explain the idea. Although in commercial tools it doesn't do the same.
t
@Amro Tork Yes, I read that link. But that doesn't help.
The "blank_circuit" only replace the extracted netlist from a layout cell by an empty one ... but it still runs the extraction first. And if the diode gets extracted at the wrong hierarchy level, then it doesn't get blanked.
I've started a LVS run on our top level where I added 
blank_circuit
on every cell below the sub cell ... it's been running extraction for the past 4 hours and there is nothing in the top level except for metal and vias, it's pure wiring.
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