Is there a way to tell magic during spice extraction that if two ports/pins have the same name, to consider them connected ( in this case two power pins that will be connected through PDN one layer above ... )

@tnt Yes, but… The default extraction connects all virtual nets (nets with the same text but not connected) at every level. The

extract unique

directive does not connect virtual nets at any level and instead add adds a

_uqX

suffix to the end of each unconnected net (in theory - I believe there are still times where nets actually connected across hierarchies etc. are renamed.). This changes the actual magic database, but this change is irrelevant if the input is gds. Be careful when using this directive with mag files. The

extract unique notopports

directive virtually connects just the top level ports. Unconnected ports in subcells will still be renamed, but the top level will have the unconnected nets extracted as one net in the final netlist. The LVS system in precheck uses

extract unique

(no virtual nets) by default, but

extract unique notopports

for analog designs. [analog designs are those that have

analog

in the top cellname]. It is possible to override the defaults by adding

"EXTRACT_TYPE": "analog"

or

"EXTRACT_TYPE": "digital"

to the

lvs_config.json

file. Be careful when using hierarchical

lvs_config.json

files because the extract type may be unexpectedly propagated to to higher levels. However, as to what you are experiencing, I think the best solution is to let magic extract the unconnected nets in subcells as separate ports that are connected at the parent level. netgen should resolve the differences automatically by flattening the levels with unmatched ports. The LVS results for the cell with virtual ports should be pretty easy to check - just an unmatch in port names, but if you wanted to avoid that you can pre-flatten the cell in LVS (netgen) with the

LVS_FLATTEN

directive in the

lvs_config.json

file. If you are experiencing problems, please let us know.

Yeah, just had to set

MAGIC_NO_EXT_UNIQUE

to 1.

Yeah, just had to set

MAGIC_NO_EXT_UNIQUE

to 1.

Be warned that this may extract a netlist that does not match the layout. For example, if the unconnected ports with the same name are not connected in a parent hierarchy, the extracted netlist will still show them as connected. But I don’t know if there is another solution when doing abstracted LVS as in openlane. One solution might be to create a source schematic that has separate ports and rename the layout accordingly. (for example,

vdda1_1

,

vdda1_2

). Don’t know if this is applicable to digital designs.

Yeah can't really do that in the default openlane flow. Also wouldn't be accepted by tiny tapeout top level integration.

I see. Should be able to catch any problems if you run the full device level LVS in precheck.