Hi all. Im trying to synthesise a 4b counter using Yosys. According to the below link I need a liberty file to do this. However, when I look at the .lib files in /pdk/SW130/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib, I see lots of them, as shown below. Which one do I use? Is there a general one? Does anyone have an example where they are performed such a synthesis? Note: I am an analog guy so total newbie at this synthesis stuff :-)! https://github.com/YosysHQ/yosys/blob/main/README.md#getting-started

Thos are all the different timing corners.

Thanks Sylvain. That seems to have worked in that my sythesized netlist (synth.v) appears to resemble a 4b counter (4 DFF's with xors). However, Im no expert - does it look reasonable to you? I have attached the behavioural verilog code (counter.v) and the list of commands I used to synthesize it (yosys_commands_v1.txt). My plan is to compile synth.v using verilator to allow me to simulate it in xschem and compare its outputs with those from the behavioural model. Before I do this however, it would be good to have a more experienced person verify the synthesized netlist looks as it should. Thanks

In the PDK there is a list somewhere of cells to not use. You need to somehow feed that to yosys too because some cells are special / weird.

Ah I see. Seems I need to migrate to openlane flow now. Initial plan was to familiarise myself with all the individual steps before migrating but seems this approach might not be so practical. Is it possible to use openlane then to synthesize a counter like I am trying?

Sure. I suggest you start with openlane2 directly which is the new version. You might also want to checkout tinytapeout.com

Great! Will do. Thanks for the help.