@samarth jain: If the user area wishbone doesn't define an address, then that means it responds to all addresses in the range 0x30000000 to 0x3fffffff. If there's only one <= 32 bit register defined, then that works; it doesn't matter what address you write to or read from. They'll all behave like the same address. On the side of the SoC, it filters the data and acknowledge signals so that the user project doesn't see any reads or writes outside of that address range.

but I do make ack 1 if address is sent by master. I just modified the example code on user proj example and added condition for specific address of slave

I was going by the fact that no

ack

signal showed up in the simulation scope trace. Is the

ready

signal properly connected to the wishbone

wbs_ack_o

?