I edited the counter user proj example as follows but I dont see any data on the given address on cocotb simulator @Tim Edwards any idea pls?

module counter #(
    parameter BITS = 16
)(
    input clk,
    input reset,
    input valid,
    input [3:0] wstrb,
    input [BITS-1:0] wdata,
    input [BITS-1:0] la_write,
    input [BITS-1:0] la_input,
    input [31:0] address,  // Address input for Wishbone address
    output reg ready,
    output reg [BITS-1:0] rdata,
    output reg [BITS-1:0] count
);

    // Define base address and offsets for the counter
    localparam BASE_ADDR     = 32'h30000000;  // Wishbone slave base address
    localparam READ_OFFSET   = 32'h00000000;  // Offset for reading
    localparam WRITE_OFFSET  = 32'h00000004;  // Offset for writing

    always @(posedge clk) begin
        if (reset) begin
            count <= 1'b0;
            ready <= 1'b0;
        end else begin
            ready <= 1'b0;

            // Increment counter when no external write is happening
            if (~|la_write) begin
                count <= count + 1'b1;
            end

            // Check if a valid transaction is happening
            if (valid && !ready) begin
                ready <= 1'b1;

                // Handle read and write operations based on the address
                if (address == (BASE_ADDR + READ_OFFSET)) begin
                    // Reading the counter value
                    rdata <= count;
                end else if (address == (BASE_ADDR + WRITE_OFFSET)) begin
                    // Writing to the counter based on `wstrb` signals
                    if (wstrb[0]) count[7:0]   <= wdata[7:0];
                    if (wstrb[1]) count[15:8]  <= wdata[15:8];
                end else begin
                    // Unknown address, transaction not ready
                    ready <= 1'b0;
                end
            end

            // Handle logic analyzer (LA) writes if necessary
            else if (|la_write) begin
                count <= la_write & la_input;
            end
        end
    end

endmodule