Hi <@U03B029DKU5>, <@U01TXC57TJM>, <@U0506JWMLA1>,...
# ieee-sscs-dc-23j
Juan Sebastian Moya
10/02/2024, 1:24 AMHi @aquiles viza, @Deni Alves, @Gabriel Maranhão, @Jorge Marin, @Atif Khan, @Akira Tsuchiya, and @Junbeom Park.
@mehdi and @Boris Murmann would like to meet with the team leaders to discuss the next steps. I sent also an email to each team leader with this information.
Can you join the Chipathon 2024 on Thursday 3rd October, at 11 am EST?
Please let us know if it fits your schedule.
Kind regards,
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Gabriel Maranhão
10/02/2024, 1:29 AMYes, I can. Please send the link to the meeting as I'm not participating on the 2024 Chipathon.
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Junbeom Park
10/02/2024, 1:30 AMIt's fine with me.
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Boris Murmann
10/02/2024, 1:32 AMThis time slot actually clashes with the VLSI TPC meeting, so I won't be able to join. If everyone else is available at the proposed time, I can meet with Mehdi separately.
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mehdi
10/02/2024, 1:36 AMThis is the Zoom Link: https://us06web.zoom.us/j/86772613482?pwd=gVvfU0WoBkibfXF8W9b0BbnbOSdNvi.1
We will be discussing PCB boards, packaging, and required parts. Please prepare accordingly.
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Atif Khan
10/02/2024, 3:21 AMYes we will be there. We are available from 9am to 1pm EST. ( 6pm-10pm pakistan time). It is fine for us if there is some change in schedule time.
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Akira Tsuchiya
10/02/2024, 3:57 AMYes, I am available
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Junbeom Park
10/02/2024, 3:59 AMSame here with @Atif Khan
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Boris Murmann
10/02/2024, 7:24 PMWe're currently getting quotes for chip packaging. A request for the lead designers of each chip: Please prepare a bonding diagram, similar to the attached example. The current suggestion is to use an 88-pin QFN package. I am attaching a second PDF that shows the lead frame for this package on the left side. You can cut this out, place your die in the center and then draw the bonding wires on top. Please count the bond wires and include any other important notes as shown in the example. Thanks!
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Gabriel Maranhão
10/03/2024, 2:10 AMHere are two files (.svg and .jpg) with the package for the groups to edit and place their chips, I took it from the QFN-88 "datasheet" that @Boris Murmann sent
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Gabriel Maranhão
10/07/2024, 9:38 PMI would like to start a discussion regarding the best approach for integrating the QFN-88 package into the PCB. We have two main options: traditional soldering assembly or using a test socket like the one shown in the attached files.
The QFN-88 package measures 1 cm x 1 cm, making manual soldering quite challenging. Given that we'll be working with multiple chips, rework during assembly could become complex and time-consuming. The test socket seems like a potential solution to simplify the process, but I'm unsure about its availability and concerned about its cost.
Another option could be designing the PCB to accommodate both assembly methods, though this might add complexity to the overall process.
I would appreciate your thoughts on these options.
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Boris Murmann
10/07/2024, 9:58 PMI would recommend having both options, socket and direct solder on the same board. The sockets are not all that expensive: https://www.amazon.com/ALLSOCKET-WLCSP88-NP506-088-014-SC-G-Programming-Clamshell/dp/B071RGRH85
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Jorge Marin
10/07/2024, 10:16 PMSorry, i couldn't attend the meeting but @aquiles viza updated us about the discussion, and we are finalizing the bond wire diagram - please excuse the delay
I wanted to ask about the maximum current capability per bonding wire, is there any information about this for the packaging option to be used?
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Boris Murmann
10/07/2024, 11:02 PMIt's a good fraction of 1A per bond wire (depending on the thickness used).
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Jorge Marin
10/07/2024, 11:10 PMThanks @Boris Murmann
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Gabriel Maranhão
10/08/2024, 1:42 PM@Boris Murmann @mehdi Is it acceptable for the PCB to have three or more layers? Due to the presence of both the socket and direct soldering on the same board, routing with only two layers has become challenging. Even when using auto-routing tools, they were unable to complete all the necessary connections.
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Boris Murmann
10/08/2024, 5:37 PMI would go for 4 layers. 1 for ground, one for power lines, two for routing.
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Jorge Marin
10/13/2024, 6:25 PM@Daniel Arevalos fyi
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Boris Murmann
10/15/2024, 3:54 AMI have received 2 of the 3 bonding diagrams. Any updates on the third one? We won't be able to move forward without it...
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aquiles viza
10/15/2024, 11:50 AMHi Professor Murmann, this is the bonding diagram for LTC2 team
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