#215 iho-sg13g2: libs.ref: sg13g2_io: verilog: Fix specify syntax Pull request opened by dnltz The input and output definition in the Verilog specify block were positioned in the wrong order (output to input). Change and also implement the tri-state better. Fixes #208 IHP-GmbH/IHP-Open-PDK ✅ All checks have passed 1/1 successful checks