Im trying to design a 2 stage OTA with 1.5 Vdd, I picked sky130lvt device, I tried designing it but the tail curr source has to be sized very large to meet the headroom requirements. Is there a better way to do it. Thank you

You can try a bulk-driven OTA https://bargh-project.ir/wp-content/uploads/2020/10/An-Ultra-Low-Voltage-Ultra-Low-Power-CMOS-Miller-OTA-With-Rail-to-Rail-InputOutput-Swing.pdf

Thank you. Its for BGR, Is the noise large in this

Yep. The biggest problem is this amplifier offset voltage. I recommend you to try to make it work first for 1.8 V, and identify this first design iteration minimum supply voltage it works. Later you can try to redesign it for 1.5 V.

Whats your input common mode? Anything > 0.5V for 1.5Vdd and you will struggle with a svt PMOS. You have opted to use a lvt PMOS so I presume vcm > 0.5. However, be very careful with the lvt PMOS. As per the char I reported 2 weeks ago, the spreads on the lvt PMOS were much much larger than for the other devices (dvth ~ +/-40% as opposed to +/-5%). No idea why it was so large or indeed if the lvt model can be trusted. In anycase, if it were me, I would look to try to implementing your diff pair using svt PMOS (can you increase vdd, can you reduce vcm). Otherwise, at dvth ~ +/-40%, its going to be very hard to get your amplifier working across corners.

Its for bgr so ip is around 0.75 for better gain I took min icmr as 0 used pmos diff pair. I was able to get it work but the tail should be sized very large this in tt I doubt this amplifier works in different corners. The only way I think is either increase vdd to 1.8 or move to diff architecture over all. I will implement diff pair using svt thank you for the suggestion

Are you designing a banba bandgap circuit or a conventional one? https://ieeexplore.ieee.org/document/760378

vcm = 0.75 at 27C which is going to go to ~ 0.9 at -40C => no chance of PMOS svt devices. The Banba is the right direction but still suffers from high i/p common modes. Leungs adaptation in 2002 addresses this by simply dividing down the input before it gets to the OTA. See Fig.2 of the below link. This will bring your vcm_ip as down to the 0.5V level you need. Just be careful because the input referred offset is now gained up by the resistor divider, in addition to the usual closed loop gain. But when I need to design a bandgap in this process, in an effort to stay clear of lvt PMOS, this is what I have in mind. Be great if you could give it a first shot and share the results! https://ieeexplore.ieee.org/document/991391

Even if I use resistor divider to divide vcm to half then also its impossible to design ota for vdd=1.5, using pmos svt its vt is around 0.8-1V.headroom is not enough for svt but lvt can but its process corner variation is very bad as you stated. Can you pls share the document where you did the pmos lvt variation check

Nothing is impossible:-)! Say vbe = 0.8 => divide by 2 gives vcm = 0.4V. Say vth = 1V. Size your diff pair to have vov = -0.2V (weak inversion). This will leave 300mV headroom across your tail bias device.

Is negative Vov is ok?

Thats a fair question since we see this unexpected kink at vov = -200mV. Is it normal / is it not ... investigations are on-going into this. You can always move your common mode down further than 2x to allow you to increase your vov

Busy this week due to my semesters, will complete them by next week if possible