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Hi, anyone knows how to reslolve this error while ...
# openlane
s
Hi, anyone knows how to reslolve this error while running openlane RTL, STA
v
zip and attach precheck logs
s
m
The Default error just means that this is the sample design. It’s so people don’t submit the sample design by mistake.
a
Hi @samarth jain, this is output from 
make run-precheck
which doesn't run RTL or STA. From what I understand, you've been using Cadence for both your analog blocks and your digital hardening, is that right? If so, those tools should be used to do RTL testing, GL testing, and STA. The 
openlane/*/*.sdc
files we provide in our template project repository can be used (with adaptation) to ensure good STA takes place in your Cadence flow. However, if you're experimenting with OpenLane to do your digital hardening (synthesis, PnR, and STA) and/or using our open source tools for RTL/GL simulation, then there's a specific way to do that (e.g. with 
make cocotb-verify-all-rtl
, or alternative commands for running individual tests). Is this what you want?
s
I get the following error while making user project wrapper
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vboxuser@Ubuntu-riscV-toolchain-instance:~/caravel_user_project$ sudo make user_project_wrapper
make -C openlane user_project_wrapper
Makefile:30: warning: undefined variable 'PWD'
Makefile:40: warning: undefined variable 'PWD'
Makefile:18: warning: undefined variable 'PWD'
Makefile:21: warning: undefined variable 'PWD'
Makefile:19: warning: undefined variable 'PWD'
Makefile:39: warning: undefined variable 'PWD'
make[1]: Entering directory '/home/vboxuser/caravel_user_project/openlane'
/venv/bin/volare enable 78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc
make[1]: /venv/bin/volare: No such file or directory
make[1]: *** [Makefile:90: enable-openlane-pdk] Error 127
make[1]: Leaving directory '/home/vboxuser/caravel_user_project/openlane'
make: *** [Makefile:126: user_project_wrapper] Error 2
This is the log from when I run make cocotb-verify-counter_wb-rtl
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vboxuser@Ubuntu-riscV-toolchain-instance:~/caravel_user_project$ make cocotb-verify-counter_wb-rtl
Run tag: run_28_Sep_19_50_52_34 
check update for docker image efabless/dv:cocotb.
<http://docker.io/efabless/dv:cocotb|docker.io/efabless/dv:cocotb>
Start running test:  RTL-counter_wb 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
/home/vboxuser/caravel_user_project/verilog/dv/cocotb/sim/run_28_Sep_19_50_52_34/RTL-compilation/sim.vvp: Unable to open input file.
Error: Fail to compile the verilog code for more info refer to /home/vboxuser/caravel_user_project/verilog/dv/cocotb/sim/run_28_Sep_19_50_52_34/RTL-compilation/compilation.log
┏━━━━━━━━━━━━┳━━━━━━━━┳━━━━━━━━━━━━┳━━━━━━━━━━━━┳━━━━━━━━━━━┳━━━━━━━━┳━━━━━━━━━┓
┃ Total      ┃ Passed ┃ Failed     ┃ Unknown    ┃ duration  ┃        ┃         ┃
┡━━━━━━━━━━━━╇━━━━━━━━╇━━━━━━━━━━━━╇━━━━━━━━━━━━╇━━━━━━━━━━━╇━━━━━━━━╇━━━━━━━━━┩
│ 1          │ 0      │ 1          │ 0          │ 0:00:05.… │        │         │
│            │        │            │            │           │        │         │
│ Test       │ status │ start      │ end        │ duration  │ p/f    │ seed    │
│ RTL-count… │ done   │ 19:50:55(… │ 19:51:00(… │ 0:00:05.… │ failed │ unknown │
└────────────┴────────┴────────────┴────────────┴───────────┴────────┴─────────┘
vboxuser@Ubuntu-riscV-toolchain-instance:~/caravel_user_project$
rtl-compilation-log.txt
a
Hi @samarth jain, you must do the "make setup" step first. I had sent you instructions for this previously in our DM that includes unsetting some environment variables.
Without that step, "make user_project_wrapper" and the cocotb tests will not work.
Also, don't use "sudo"
s
Hi, when we run openlane make user project wrapper, does it do STA for user project exmaple and complete sub modules? or only for top module user project wrapper? i dont see any STA timing violations in my design and its bit weird for me . @Mitch Bailey
m
I think it’s only for the synthesized blocks and not for the hard macros. I think the hard macro timing requires need to be included in a separate sdc file, but I’m not an expert.
a
@samarth jain I think @Marwan Abbas might be able to clarify but my understanding is that if you have hardened your macro (e.g. user_proj_example), and it passed STA, and you then harden user_project_wrapper including this macro and it too passed STA, then it has already considered the timing requirements of user_proj_example by virtue of the spef/lib timing data, so you should be good. This assumes you have specified the correct CLOCK_PORT/CLOCK_NET in your config.json file(s), and that you are not doing something in your overall design & integration that would make our supplied default SDC files inaccurate.
One more thing you can do is to run full-chip STA, as an extra check. I think we've discussed this before but to reiterate, it is covered here: https://github.com/efabless/caravel_user_project/blob/main/docs/source/index.md#running-timing-analysis-on-existing-projects -- Just be aware that since you last ran "make setup", we have updated the repo to fix a full-chip STA issue, so you probably need to run "make setup" in your project again -- and prior to running "make setup" (just to be extra careful about not replacing any existing PDK data you've got elsewhere on your system) you might want to do the following so that "make setup" uses its proper LOCAL defaults:
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unset MPW_TAG PDK PDK_ROOT MCW_ROOT OPENLANE_ROOT
unset OPENLANE_IMAGE_NAME OPENLANE_RUN_TAG OPENLANE_TAG
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