open-source-silicon.dev

So I'm looking at parasitics in sky130, specifically met1 traces running parallel to each other. 0.15u wide, 0.35u distance (edge to edge).

The google docs lists 44.74 aF/um for sidewall capacitance at 1um distance. So scaling that to 0.35u you'd get something like ~ 127 aF/um

AFAICT. However, given the traces are quite thin (their width is actually not even half their layer thickness), I would think that the class parallel plate capacitance would give a fair approximation. So going to that for a 1um segment you get, 8.854e-12 * 4.5 * 0.36e-6 * 1.00e-6 / 0.35e-6 ~= 41 aF/um.

I mean I didn't expect the two numbers to match exactly but it's quite the difference ...

Fringe capacitance can be larger than area capacitance for interconnects.

<@U016EM8L91B> Upon checking magic's tech files, the values in there don't match the google docs spread sheets.

Last time they were update was in <https://github.com/RTimothyEdwards/open_pdks/commit/5ed94ffe0059046164bfb97f670fab648fa90602>  and the commit message only talks about klayout, no mention of where/why those were modified ...

<@U016HU5HK8V>:  I struggled with that for a long time before working out a solution via field solver, which can be found at <https://github.com/RTimothyEdwards/capiche>
The bottom line is that the (1/d) relationship does not hold up very well for wires, and this can be seen clearly from the field equation solver results when plotted against an ideal (1/d) curve.
The modeling ends up being closest to (1/(d+offset)) where "offset" can be surprisingly large.
The modeling for metal1 sidewall is 44 aF/um / (d + 0.25um);  the 44 aF/um number only gives the magnitude.
For your example, that yields 44 / (0.35 + 0.25) = 73 aF/um.  That's much less than 127 but no, it doesn't match what you'd get from an ideal parallel plate equation.
If you draw out the wires in a layout at 1um length, feed that to magic, and extract with parasitics, you get the 73 aF value:
```C0 m1_0_0# m1_100_0# 0.073333f```

Oh, interesting, I'll have a look at capiche, I was trying to get FastCap2 to run right now :sweat_smile:

I had also estimated around ~ 80 aF using the equations for 2 cylindrical wire, which is a bit closer.

Thank you very much for the explanation and the pointer to capiche !

If you have any suggestions for improvements to capiche, talk to <@U02G0CLTGTH>.
We are working on adding the IHP process stack to capiche and getting the results for parasitic modeling of the SG13G2 stackup.
Capiche was written to solve an immediate problem, and is not especially user-friendly.  I was hoping that Leo could help with that part.

FYI, I have been using "FasterCap" in 2D mode, which is considerably easier to set up an input file for than a full 3D solution.  And the answers are automatically in unit capacitance per length.